Robert H. M. van Veldhoven
Orcid: 0000-0001-7815-2010
According to our database1,
Robert H. M. van Veldhoven
authored at least 31 papers
between 2002 and 2022.
Collaborative distances:
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Bibliography
2022
A 590 µW, 106.6 dB SNDR, 24 kHz BW Continuous-Time Zoom ADC with a Noise-Shaping 4-bit SAR ADC.
Proceedings of the 48th IEEE European Solid State Circuits Conference, 2022
2021
An Area-Efficient SAR ADC With Mismatch Error Shaping Technique Achieving 102-dB SFDR 90.2-dB SNDR Over 20-kHz Bandwidth.
IEEE Trans. Very Large Scale Integr. Syst., 2021
IEEE J. Solid State Circuits, 2021
2020
IEEE J. Solid State Circuits, 2020
IEEE J. Solid State Circuits, 2020
Proceedings of the IEEE Symposium on VLSI Circuits, 2020
9.8 A Low-Cost 4-Channel Reconfigurable Audio Interface for Car Entertainment Systems.
Proceedings of the 2020 IEEE International Solid- State Circuits Conference, 2020
23.4 A 28W -108.9dB/-102.2dB THD/THD+N Hybrid ΔΣ-PWM Class-D Audio Amplifier with 91% Peak Efficiency and Reduced EMI Emission.
Proceedings of the 2020 IEEE International Solid- State Circuits Conference, 2020
2019
Proceedings of the 2019 Symposium on VLSI Circuits, Kyoto, Japan, June 9-14, 2019, 2019
2018
IEEE J. Solid State Circuits, 2018
IEEE J. Solid State Circuits, 2018
Proceedings of the 2018 IEEE International Solid-State Circuits Conference, 2018
A phase-domain readout circuit for a CMOS-compatible thermal-conductivity-based carbon dioxide sensor.
Proceedings of the 2018 IEEE International Solid-State Circuits Conference, 2018
2017
IEEE J. Solid State Circuits, 2017
2016
A Ratiometric Readout Circuit for Thermal-Conductivity-Based Resistive CO<sub>2</sub> Sensors.
IEEE J. Solid State Circuits, 2016
Proceedings of the 2016 IEEE International Solid-State Circuits Conference, 2016
2015
Proceedings of the ESSCIRC Conference 2015, 2015
2014
17.5 A 0.07mm<sup>2</sup> 2-channel instrumentation amplifier with 0.1% gain matching in 0.16μm CMOS.
Proceedings of the 2014 IEEE International Conference on Solid-State Circuits Conference, 2014
2013
Proceedings of the 5th IEEE International Workshop on Advances in Sensors and Interfaces, 2013
Proceedings of the 2013 IEEE International Solid-State Circuits Conference, 2013
A 0.1-mm<sup>2</sup> 3-channel area-optimized ΣΔ ADC in 0.16-µm CMOS with 20-kHz BW and 86-dB DR.
Proceedings of the ESSCIRC 2013, 2013
2011
A 14 bit 200 MS/s DAC With SFDR > 78 dBc, IM3 < - 83 dBc and NSD < - 163 dBm/Hz Across the Whole Nyquist Band Enabled by Dynamic-Mismatch Mapping.
IEEE J. Solid State Circuits, 2011
2008
Proceedings of the 2008 IEEE International Solid-State Circuits Conference, 2008
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008
2007
A 56 mW Continuous-Time Quadrature Cascaded ΣΔ Modulator With 77 dB DR in a Near Zero-IF 20 MHz Band.
IEEE J. Solid State Circuits, 2007
Proceedings of the 2007 IEEE International Solid-State Circuits Conference, 2007
A 56mW CT Quadrature Cascaded ΣΔ Modulator with 77dB DR in a Near Zero-IF 20MHz Band.
Proceedings of the 2007 IEEE International Solid-State Circuits Conference, 2007
2006
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006
Proceedings of the 13th IEEE International Conference on Electronics, 2006
2003
A triple-mode continuous-time ΣΔ modulator with switched-capacitor feedback DAC for a GSM-EDGE/CDMA2000/UMTS receiver.
IEEE J. Solid State Circuits, 2003
2002
A 3.3-mW ΣΔ modulator for UMTS in 0.18-μm CMOS with 70-dB dynamic range in 2-MHz bandwidth.
IEEE J. Solid State Circuits, 2002