Kambiz Kaviani

According to our database1, Kambiz Kaviani authored at least 17 papers between 2001 and 2021.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

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PhD thesis 
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Links

On csauthors.net:

Bibliography

2021
An Echo-Cancelling Front-End for 112Gb/s PAM-4 Simultaneous Bidirectional Signaling in 14nm CMOS.
Proceedings of the IEEE International Solid-State Circuits Conference, 2021

2014
A 6.4-Gb/s Near-Ground Single-Ended Transceiver for Dual-Rank DIMM Memory Interface Systems.
IEEE J. Solid State Circuits, 2014

An Adaptive Body-Biased Clock Generation System in 28nm CMOS.
Proceedings of the 2014 27th International Conference on VLSI Design, 2014

2013
A 0.4-mW/Gb/s Near-Ground Receiver Front-End With Replica Transconductance Termination Calibration for a 16-Gb/s Source-Series Terminated Transceiver.
IEEE J. Solid State Circuits, 2013

A 6.4Gb/s near-ground single-ended transceiver for dual-rank DIMM memory interface systems.
Proceedings of the 2013 IEEE International Solid-State Circuits Conference, 2013

A 0.94mW/Gb/s 22Gb/s 2-tap partial-response DFE receiver in 40nm LP CMOS.
Proceedings of the 2013 IEEE International Solid-State Circuits Conference, 2013

2012
A Tri-Modal 20-Gbps/Link Differential/DDR3/GDDR5 Memory Interface.
IEEE J. Solid State Circuits, 2012

A 12.8-Gb/s/link Tri-Modal Single-Ended Memory Interface.
IEEE J. Solid State Circuits, 2012

A 4.1-pJ/b, 16-Gb/s Coded Differential Bidirectional Parallel Electrical Link.
IEEE J. Solid State Circuits, 2012

A 0.4mW/Gb/s 16Gb/s near-ground receiver front-end with replica transconductance termination calibration.
Proceedings of the 2012 IEEE International Solid-State Circuits Conference, 2012

A 4.1pJ/b 16Gb/s coded differential bidirectional parallel electrical link.
Proceedings of the 2012 IEEE International Solid-State Circuits Conference, 2012

A 27-Gb/s, 0.41-mW/Gb/s 1-tap predictive decision feedback equalizer in 40-nm low-power CMOS.
Proceedings of the IEEE 2012 Custom Integrated Circuits Conference, 2012

A 6.4/3.2/1.6 Gb/s low power interface with all digital clock multiplier for on-the-fly rate switching.
Proceedings of the IEEE 2012 Custom Integrated Circuits Conference, 2012

2009
A 16 Gb/s/Link, 64 GB/s Bidirectional Asymmetric Memory Interface.
IEEE J. Solid State Circuits, 2009

2008
Clocking circuits for a 16Gb/s memory interface.
Proceedings of the IEEE 2008 Custom Integrated Circuits Conference, 2008

2003
A multichannel pipeline analog-to-digital converter for an integrated 3-D ultrasound imaging system.
IEEE J. Solid State Circuits, 2003

2001
An ultrasonic volumetric scanner for image-guided surgery.
Proceedings of the CARS 2001. Computer Assisted Radiology and Surgery. Proceedings of the 15th International Congress and Exhibition, 2001


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