José E. Schutt-Ainé

Orcid: 0009-0006-0582-9346

According to our database¹, José E. Schutt-Ainé authored at least 19 papers between 1988 and 2026.

Collaborative distances:

Dijkstra number² of five.
Erdős number³ of four.

Awards

IEEE Fellow

IEEE Fellow 2007, "For contributions to modeling and simulation of distributed circuits with applications to signal integrity".

Timeline

Legend:

Book In proceedings Article PhD thesis Dataset Other

Bibliography

2026

Latency Insertion Method for Fast FinFET Simulation Based on the BSIM-CMG Model.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. I Regul. Pap., May, 2026

2023

A new pre-conditioned STDP rule and its hardware implementation in neuromorphic crossbar array.

[BibT_eX]

[DOI]

Neurocomputing, November, 2023

Modeling and Analysis of Spike Signal Sequence for Memristor Crossbar Array in Neuromorphic Chips.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. I Regul. Pap., 2023

2021

Thin-Film Transistor Simulations With the Voltage-In-Current Latency Insertion Method.

[BibT_eX]

[DOI]

IEEE Access, 2021

2020

PAM-4 Behavioral Modeling using Machine Learning via Laguerre-Volterra Expansion.

[BibT_eX]

[DOI]

Xinying Wang

Thong Nguyen

José E. Schutt-Ainé

Proceedings of the 11th IEEE Latin American Symposium on Circuits & Systems, 2020

2019

Fast Transient Simulation of High-Speed Channels Using Recurrent Neural Network.

[BibT_eX]

[DOI]

CoRR, 2019

An Improved Algorithm for Drift Diffusion Transport and Its Application on Large Scale Parallel Simulation of Resistive Random Access Memory Arrays.

[BibT_eX]

[DOI]

IEEE Access, 2019

Fully Coupled Electrothermal Simulation of Large RRAM Arrays in the "Thermal-House".

[BibT_eX]

[DOI]

IEEE Access, 2019

LIM Algorithms for MOSFET Models.

[BibT_eX]

[DOI]

José E. Schutt-Ainé

Patrick Goh

Proceedings of the 10th IEEE Latin American Symposium on Circuits & Systems, 2019

2018

A 10-Gb/s/ch, 0.6-pJ/bit/mm Power Scalable Rapid-ON/OFF Transceiver for On-Chip Energy Proportional Interconnects.

[BibT_eX]

[DOI]

IEEE J. Solid State Circuits, 2018

2013

Phase-locked loop simulations using the latency insertion method.

[BibT_eX]

[DOI]

José E. Schutt-Ainé

Patrick Goh

Proceedings of the 4th IEEE Latin American Symposium on Circuits and Systems, 2013

2007

Topological realizability conditions and their interpretation for admittance matrices of an MTL system with mode delays.

[BibT_eX]

[DOI]

Josh G. Nickel

José E. Schutt-Ainé

J. Frankl. Inst., 2007

2001

High-frequency characterization of twisted-pair cables.

[BibT_eX]

[DOI]

José E. Schutt-Ainé

IEEE Trans. Commun., 2001

Scanning the issue interconnections - addressing the next challenge of IC technology (part II: design, characterization, and modeling).

[BibT_eX]

[DOI]

José E. Schutt-Ainé

Sung-Mo Kang

Proc. IEEE, 2001

Interconnections-addressing the next challenge of IC technology (part I: integration and packaging trends).

[BibT_eX]

[DOI]

José E. Schutt-Ainé

Sung-Mo Kang

Proc. IEEE, 2001

1997

Transient analysis of diode switching circuits using asymptotic waveform evaluation.

[BibT_eX]

[DOI]

Wendemagegnehu T. Beyene

José E. Schutt-Ainé

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1997

1993

Modeling Interconnections with Nonlinear Discontinuities.

[BibT_eX]

José E. Schutt-Ainé

Kyung-soo Oh

Proceedings of the 1993 IEEE International Symposium on Circuits and Systems, 1993

Difference Model Approach for the Transient Simulation of Transmission Lines.

[BibT_eX]

Dimitri Kuznetsov

José E. Schutt-Ainé

Proceedings of the 1993 IEEE International Symposium on Circuits and Systems, 1993

1988

Modeling and Simulation of High-Speed Digital Circuit Interconnections

[BibT_eX]

[DOI]

José E. Schutt-Ainé

PhD thesis, 1988

José E. Schutt-Ainé

Awards

IEEE Fellow

Timeline

Legend:

Links

Online presence:

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Bibliography

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