Wendemagegnehu T. Beyene

According to our database1, Wendemagegnehu T. Beyene authored at least 16 papers between 1997 and 2013.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Dataset
Other 

Links

On csauthors.net:

Bibliography

2013
A 0.4-mW/Gb/s Near-Ground Receiver Front-End With Replica Transconductance Termination Calibration for a 16-Gb/s Source-Series Terminated Transceiver.
IEEE J. Solid State Circuits, 2013

2012
A Tri-Modal 20-Gbps/Link Differential/DDR3/GDDR5 Memory Interface.
IEEE J. Solid State Circuits, 2012

A 12.8-Gb/s/link Tri-Modal Single-Ended Memory Interface.
IEEE J. Solid State Circuits, 2012

A 4.1-pJ/b, 16-Gb/s Coded Differential Bidirectional Parallel Electrical Link.
IEEE J. Solid State Circuits, 2012

A 0.4mW/Gb/s 16Gb/s near-ground receiver front-end with replica transconductance termination calibration.
Proceedings of the 2012 IEEE International Solid-State Circuits Conference, 2012

A 4.1pJ/b 16Gb/s coded differential bidirectional parallel electrical link.
Proceedings of the 2012 IEEE International Solid-State Circuits Conference, 2012

2011
On overcoming the limitations of single-ended signaling for graphics memory interfaces.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2011

2009
A 16 Gb/s/Link, 64 GB/s Bidirectional Asymmetric Memory Interface.
IEEE J. Solid State Circuits, 2009

2007
Application of Artificial Neural Networks to Statistical Analysis and Nonlinear Modeling of High-Speed Interconnect Systems.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2007

Low-Order Rational Approximation of Interconnects Using Neural-Network Based Pole-Clustering Techniques.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007

System Co-Design and Co-Analysis Approach to Implementing the XDR Memory System of the Cell Broadband Engine Processor; Realizing 3.2 Gbps Data Rate per Memory Lane in Low Cost, High Volume Production.
Proceedings of the 12th Conference on Asia South Pacific Design Automation, 2007

2003
Modeling and Analysis of Power Distribution Networks for Gigabit Applications.
IEEE Trans. Mob. Comput., 2003

Modeling and Analysis of Power Distribution Networks for Gigabit Applications.
Proceedings of the 4th International Symposium on Quality of Electronic Design (ISQED 2003), 2003

2002
On the Use of Windows for Accurate Analysis of Package Interconnects.
Proceedings of the 3rd International Symposium on Quality of Electronic Design, 2002

1997
Model-Order Reduction Techniques for Circuits and Interconnects Simulation
PhD thesis, 1997

Transient analysis of diode switching circuits using asymptotic waveform evaluation.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1997


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