José Ernesto Rayas-Sánchez

Orcid: 0000-0003-2611-5618

According to our database1, José Ernesto Rayas-Sánchez authored at least 14 papers between 2004 and 2022.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of five.

Timeline

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Bibliography

2022
Frequency- and Time-Domain Yield Optimization of a Power Delivery Network Subject to Large Decoupling Capacitor Tolerances.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022

2020
A Holistic Formulation for System Margining and Jitter Tolerance Optimization in Industrial Post-Silicon Validation.
IEEE Trans. Emerg. Top. Comput., 2020

Machine Learning Techniques and Space Mapping Approaches to Enhance Signal and Power Integrity in High-Speed Links and Power Delivery Networks.
Proceedings of the 11th IEEE Latin American Symposium on Circuits & Systems, 2020

2019
Post-Silicon Receiver Equalization Metamodeling by Artificial Neural Networks.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2019

A tool for the automatic generation and analysis of regular analog layout modules.
Integr., 2019

2018
Direct optimization of a PCI express link equalization in industrial post-silicon validation.
Proceedings of the 19th IEEE Latin-American Test Symposium, 2018

Jitter tolerance acceleration using the golden section optimization technique.
Proceedings of the 9th IEEE Latin American Symposium on Circuits & Systems, 2018

Transmitter and Receiver Equalizers Optimization Methodologies for High-Speed Links in Industrial Computer Platforms Post-Silicon Validation.
Proceedings of the IEEE International Test Conference, 2018

2017
Analysis of the implications of stacked devices in nano-scale technologies for analog applications.
Proceedings of the 18th IEEE Latin American Test Symposium, 2017

Design of experiments implementation towards optimization of power distribution networks.
Proceedings of the 8th IEEE Latin American Symposium on Circuits & Systems, 2017

2015
Impedance matching analysis and EMC validation of a low-cost PCB differential interconnect.
Proceedings of the 16th Latin-American Test Symposium, 2015

2014
A digital predistortion technique based on a NARX network to linearize GaN class F power amplifiers.
Proceedings of the IEEE 57th International Midwest Symposium on Circuits and Systems, 2014

2013
Systematic configuration of coarsely discretized 3D EM solvers for reliable and fast simulation of high-frequency planar structures.
Proceedings of the 4th IEEE Latin American Symposium on Circuits and Systems, 2013

2004
A frequency-domain approach to interconnect crosstalk simulation and minimization.
Microelectron. Reliab., 2004


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