Nagib Hakim

According to our database1, Nagib Hakim authored at least 25 papers between 2004 and 2023.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

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PhD thesis 
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Links

On csauthors.net:

Bibliography

2023
Fusing Temporal Graphs into Transformers for Time-Sensitive Question Answering.
Proceedings of the Findings of the Association for Computational Linguistics: EMNLP 2023, 2023

2022
Thrill-K Architecture: Towards a Solution to the Problem of Knowledge Based Understanding.
Proceedings of the Artificial General Intelligence - 15th International Conference, 2022

TempoQR: Temporal Question Reasoning over Knowledge Graphs.
Proceedings of the Thirty-Sixth AAAI Conference on Artificial Intelligence, 2022

2021
TempoQR: Temporal Question Reasoning over Knowledge Graphs.
CoRR, 2021

Semi-supervised Interactive Intent Labeling.
CoRR, 2021

2020
A Holistic Formulation for System Margining and Jitter Tolerance Optimization in Industrial Post-Silicon Validation.
IEEE Trans. Emerg. Top. Comput., 2020

2019
Post-Silicon Receiver Equalization Metamodeling by Artificial Neural Networks.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2019

2018
Direct optimization of a PCI express link equalization in industrial post-silicon validation.
Proceedings of the 19th IEEE Latin-American Test Symposium, 2018

Transmitter and Receiver Equalizers Optimization Methodologies for High-Speed Links in Industrial Computer Platforms Post-Silicon Validation.
Proceedings of the IEEE International Test Conference, 2018

2016
A 65 nm Programmable ANalog Device Array (PANDA) for Analog Circuit Emulation.
IEEE Trans. Circuits Syst. I Regul. Pap., 2016

2014
Effective Post-Silicon Validation of System-on-Chips Using Quick Error Detection.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2014

2013
Programmable ANalog Device Array (PANDA): A Methodology for Transistor-Level Analog Emulation.
IEEE Trans. Circuits Syst. I Regul. Pap., 2013

Innovative practices session 1C: Post-silicon validation.
Proceedings of the 31st IEEE VLSI Test Symposium, 2013

Overcoming post-silicon validation challenges through quick error detection (QED).
Proceedings of the Design, Automation and Test in Europe, 2013

2012
Quick detection of difficult bugs for effective post-silicon validation.
Proceedings of the 49th Annual Design Automation Conference 2012, 2012

A hybrid electrical-behavioral modeling approach for pre- and post-silicon electrical validation.
Proceedings of the IEEE 2012 Custom Integrated Circuits Conference, 2012

Bug localization techniques for effective post-silicon validation.
Proceedings of the 17th Asia and South Pacific Design Automation Conference, 2012

2011
Programmable analog device array (PANDA): a platform for transistor-level analog reconfigurability.
Proceedings of the 48th Design Automation Conference, 2011

2010
QED: Quick Error Detection tests for effective post-silicon validation.
Proceedings of the 2011 IEEE International Test Conference, 2010

Post-silicon validation challenges: how EDA and academia can help.
Proceedings of the 47th Design Automation Conference, 2010

2008
FPGA family composition and effects of specialized blocks.
Proceedings of the FPL 2008, 2008

2005
Measurements and modeling of intrinsic fluctuations in MOSFET threshold voltage.
Proceedings of the 2005 International Symposium on Low Power Electronics and Design, 2005

Statistical static timing analysis: how simple can we get?
Proceedings of the 42nd Design Automation Conference, 2005

2004
Coping with Uncertainty.
Proceedings of the 5th International Symposium on Quality of Electronic Design (ISQED 2004), 2004

The care and feeding of your statistical static timer.
Proceedings of the 2004 International Conference on Computer-Aided Design, 2004


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