José María López-Villegas

According to our database, José María López-Villegas authored at least 19 papers between 2009 and 2022.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2022

Microstrip-Fed 3D-Printed H-Sectorial Horn Phased Array.

Ivan Zhou, Lluís Pradell, José María López-Villegas, Neus Vidal, Miquel Albert, Lluis Jofre, Jordi Romeu

Sensors, 2022

Very compact 3D-printed folded branch-line hybrid coupler based on loaded helical-microstrip transmission lines.

Arnau Salas Barenys, Neus Vidal, José María López-Villegas

Integr., 2022

3D-Printed Broadband Power Divider Based on Helical-Microstrip Transmission Line Segments.

José María López-Villegas, Neus Vidal, Arnau Salas Barenys

IEEE Access, 2022

2020

A Multilevel Bottom-Up Optimization Methodology for the Automated Synthesis of RF Systems.

Fábio Passos, Elisenda Roca, Javier J. Sieiro, Rafaella Fiorelli, Rafael Castro-López, José María López-Villegas, Francisco V. Fernández

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020

3D-Printed UHF-RFID Tag for Embedded Applications.

Neus Vidal, José María López-Villegas, Jordi Romeu, Arnau Salas Barenys, Aleix Garcia-Miquel, Giselle González-López, Lluis Jofre

IEEE Access, 2020

Design and Characterization of Non-planar 3D-printed Passive UHF-RFID Tag.

Neus Vidal, Arnau Salas Barenys, Aleix Garcia, Jordi Romeu, Giselle González, Lluis Jofre, José María López-Villegas

Proceedings of the XXXV Conference on Design of Circuits and Integrated Systems, 2020

Compact 3D-Printed Folded Branch-Line Hybrid Coupler based on Helical-Microstrip Transmission Lines.

Arnau Salas Barenys, Neus Vidal, José María López-Villegas

Proceedings of the XXXV Conference on Design of Circuits and Integrated Systems, 2020

2019

Analysis and Optimization of Multi-Winding Toroidal Inductors for Use in Multilayered Technologies.

Neus Vidal, José María López-Villegas, Jesús A. del Alamo

IEEE Access, 2019

3D Printed 5-Order Butterworth Passive Filter with Conical Inductors for RF Broadband Applications.

Arnau Salas Barenys, Neus Vidal, José María López-Villegas

Proceedings of the XXXIV Conference on Design of Circuits and Integrated Systems, 2019

2018

Quasi-static PEEC planar solver using a weighted combination of 2D and 3D analytical Green's functions and a predictive meshing generator.

Saiyd Ahyoune, Javier J. Sieiro, Tomás Carrasco Carrillo, Neus Vidal, José María López-Villegas, Elisenda Roca, Francisco V. Fernández

Integr., 2018

Fabrication of Full-3D Printed Electronics RF Passive Components and Circuits.

Arnau Salas Barenys, Neus Vidal, Javier J. Sieiro, José María López-Villegas, B. Medina-Rodriguez, F. M. Ramos

Proceedings of the 14th Conference on Ph.D. Research in Microelectronics and Electronics, 2018

2017

An Automated Design Methodology of RF Circuits by Using Pareto-Optimal Fronts of EM-Simulated Inductors.

Reinier Gonzalez-Echevarria, Elisenda Roca, Rafael Castro-López, Francisco V. Fernández, Javier J. Sieiro, José María López-Villegas, Neus Vidal

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2017

Extending the frequency range of quasi-static electromagnetic solvers.

Saiyd Ahyoune, Javier J. Sieiro, Tomás Carrasco Carrillo, Neus Vidal, José María López-Villegas, Elisenda Roca, Francisco V. Fernández

Proceedings of the 14th International Conference on Synthesis, 2017

2014

Automated Generation of the Optimal Performance Trade-Offs of Integrated Inductors.

Reinier Gonzalez-Echevarria, Rafael Castro-López, Elisenda Roca, Francisco V. Fernández, Javier J. Sieiro, Neus Vidal, José María López-Villegas

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2014

2010

Erratum to the Special Section on DCIS 2006 [Integration, the VLSI Journal, Volume 42, Issue 3, June 2009].

Manel Puig, José María López-Villegas, Atila Herms

Integr., 2010

Low-power current-reused RF front-end based on optimized transformers topology.

Ignacio Gil, Ignasi Cairó, Javier J. Sieiro, José María López-Villegas

Integr., 2010

Optimized passive devices for low-power LNA design.

Ignacio Gil, Raúl Fernández, Javier J. Sieiro, José María López-Villegas

Proceedings of the 17th IEEE International Conference on Electronics, 2010

2009

CMOS single-ended-to-differential low-noise amplifier.

Tomás Carrasco Carrillo, José Gabriel Macias-Montero, Aitor Osorio Martí, Javier Sieiro Córdoba, José María López-Villegas

Integr., 2009

A 19GHz, 250pJ/bit non-linear BPSK demodulator in 90nm CMOS.

José Gabriel Macias-Montero, H. Yan, Atef Akhnoukh, Leo C. N. de Vreede, John R. Long, José María López-Villegas, John J. Pekarik

Proceedings of the 35th European Solid-State Circuits Conference, 2009