Rafaella Fiorelli

Orcid: 0000-0001-9434-4397

According to our database1, Rafaella Fiorelli authored at least 26 papers between 2004 and 2020.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

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Bibliography

2020
A Sub- $\mu$ W Reconfigurable Front-End for Invasive Neural Recording That Exploits the Spectral Characteristics of the Wideband Neural Signal.
IEEE Trans. Circuits Syst. I Fundam. Theory Appl., 2020

Offset-Calibration With Time-Domain Comparators Using Inversion-Mode Varactors.
IEEE Trans. Circuits Syst. II Express Briefs, 2020

A Multilevel Bottom-Up Optimization Methodology for the Automated Synthesis of RF Systems.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020

Charge-Redistribution Based Quadratic Operators for Neural Feature Extraction.
IEEE Trans. Biomed. Circuits Syst., 2020

Normalized Nonlinear Semiempirical MOST Model Used in Monolithic RF Class A-to-C PAs.
Circuits Syst. Signal Process., 2020

2019
A Sub-µW Reconfigurable Front-End for Invasive Neural Recording.
Proceedings of the 10th IEEE Latin American Symposium on Circuits & Systems, 2019

A High TCMRR, Inherently Charge Balanced Bidirectional Front-End for Multichannel Closed-Loop Neuromodulation.
Proceedings of the 2019 IEEE Biomedical Circuits and Systems Conference, 2019

A 32 Input Multiplexed Channel Analog Front-End with Spatial Delta Encoding Technique and Differential Artifacts Compression.
Proceedings of the 2019 IEEE Biomedical Circuits and Systems Conference, 2019

2018
All-inversion region gm/ID methodology for RF circuits in FinFET technologies.
Proceedings of the 16th IEEE International New Circuits and Systems Conference, 2018

2016
Semi-empirical RF MOST model for CMOS 65 nm technologies: Theory, extraction method and validation.
Integr., 2016

Mixed-signal quadratic operators for the feature extraction of neural signals.
Proceedings of the IEEE Biomedical Circuits and Systems Conference, 2016

A 76nW, 4kS/s 10-bit SAR ADC with offset cancellation for biomedical applications.
Proceedings of the 2016 IEEE Asia Pacific Conference on Circuits and Systems, 2016

2011
Alternate Test of LNAs Through Ensemble Learning of On-Chip Digital Envelope Signatures.
J. Electron. Test., 2011

2.4-GHz single-ended input low-power low-voltage active front-end for ZigBee applications in 90 nm CMOS.
Proceedings of the 20th European Conference on Circuit Theory and Design, 2011

Improving the Accuracy of RF Alternate Test Using Multi-VDD Conditions: Application to Envelope-Based Test of LNAs.
Proceedings of the 20th IEEE Asian Test Symposium, 2011

2010
Efficiency based design flow for fully-integrated class C RF power amplifiers in nanometric CMOS.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010

A fully differential monolithic 2.4GHZ PA for IEEE 802.15.4 based on efficiency design flow.
Proceedings of the 17th IEEE International Conference on Electronics, 2010

Low-cost signature test of RF blocks based on envelope response analysis.
Proceedings of the 15th European Test Symposium, 2010

2009
Phase noise - consumption trade-off in low power RF-LC-VCO design in micro and nanometric technologies.
Proceedings of the 22st Annual Symposium on Integrated Circuits and Systems Design: Chip on the Dunes, 2009

A BIST Solution for the Functional Characterization of RF Systems Based on Envelope Response Analysis.
Proceedings of the Eighteentgh Asian Test Symposium, 2009

2008
A 2.4GHz LNA in a 90-nm CMOS technology designed with ACM model.
Proceedings of the 21st Annual Symposium on Integrated Circuits and Systems Design, 2008

2006
Nanowatt, Sub-nS OTAs, With Sub-10-mV Input Offset, Using Series-Parallel Current Mirrors.
IEEE J. Solid State Circuits, 2006

A tool for design exploration and power optimization of CMOS RF circuits blocks.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

2005
Design and power optimization of CMOS RF blocks operating in the moderate inversion region.
Proceedings of the 18th Annual Symposium on Integrated Circuits and Systems Design, 2005

On the design of very small transconductance OTAs with reduced input offset.
Proceedings of the 18th Annual Symposium on Integrated Circuits and Systems Design, 2005

2004
Series-parallel association of transistors for the reduction of random offset in non-unity gain current mirrors.
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004


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