Francisco V. Fernández
Orcid: 0000-0001-8682-2280Affiliations:
- University of Seville, Spain
According to our database1,
Francisco V. Fernández
authored at least 136 papers
between 1992 and 2023.
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Bibliography
2023
A detailed, cell-by-cell look into the effects of aging on an SRAM PUF using a specialized test array.
Proceedings of the 19th International Conference on Synthesis, 2023
Proceedings of the 19th International Conference on Synthesis, 2023
Proceedings of the 19th International Conference on Synthesis, 2023
Proceedings of the 19th International Conference on Synthesis, 2023
Strategies for parameter extraction of the time constant distribution of time-dependent variability models for nanometer-scale devices.
Proceedings of the 19th International Conference on Synthesis, 2023
Proceedings of the 19th International Conference on Synthesis, 2023
Challenges and solutions to the defect-centric modeling and circuit simulation of time-dependent variability.
Proceedings of the IEEE International Reliability Physics Symposium, 2023
2022
On the Impact of the Biasing History on the Characterization of Random Telegraph Noise.
IEEE Trans. Instrum. Meas., 2022
Integr., 2022
A systematic approach to RTN parameter fitting based on the Maximum Current Fluctuation.
Proceedings of the 18th International Conference on Synthesis, 2022
Proceedings of the 18th International Conference on Synthesis, 2022
Proceedings of the 18th International Conference on Synthesis, 2022
Proceedings of the 18th International Conference on Synthesis, 2022
On the use of an RTN simulator to explore the quality trade-offs of a novel RTN-based PUF.
Proceedings of the 18th International Conference on Synthesis, 2022
Proceedings of the 18th International Conference on Synthesis, 2022
Proceedings of the IEEE International Symposium on Circuits and Systems, 2022
A Smart SRAM-Cell Array for the Experimental Study of Variability Phenomena in CMOS Technologies.
Proceedings of the IEEE International Reliability Physics Symposium, 2022
2021
Hierarchical Yield-Aware Synthesis Methodology Covering Device-, Circuit-, and System-Level for Radiofrequency ICs.
IEEE Access, 2021
2020
Flexible Setup for the Measurement of CMOS Time-Dependent Variability With Array-Based Integrated Circuits.
IEEE Trans. Instrum. Meas., 2020
A Multilevel Bottom-Up Optimization Methodology for the Automated Synthesis of RF Systems.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020
Synthesis of mm-Wave Wideband Receivers in 28-nm CMOS Technology for Automotive Radar Applications.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020
Chaotic Image Encryption Using Hopfield and Hindmarsh-Rose Neurons Implemented on FPGA.
Sensors, 2020
Yield-aware multi-objective optimization of a MEMS accelerometer system using QMC-based methodologies.
Microelectron. J., 2020
A robust and automated methodology for the analysis of Time-Dependent Variability at transistor level.
Integr., 2020
Ready-to-Fabricate RF Circuit Synthesis Using a Layout- and Variability-Aware Optimization-Based Methodology.
IEEE Access, 2020
Proceedings of the 15th Design & Technology of Integrated Systems in Nanoscale Era, 2020
2019
Two-Step RF IC Block Synthesis With Preoptimized Inductors and Full Layout Generation In-the-Loop.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2019
A two-step surrogate modeling strategy for single-objective and multi-objective optimization of radiofrequency circuits.
Soft Comput., 2019
A Versatile CMOS Transistor Array IC for the Statistical Characterization of Time-Zero Variability, RTN, BTI, and HCI.
IEEE J. Solid State Circuits, 2019
Optimization and CMOS design of chaotic oscillators robust to PVT variations: INVITED.
Integr., 2019
TiDeVa: A Toolbox for the Automated and Robust Analysis of Time-Dependent Variability at Transistor Level.
Proceedings of the 16th International Conference on Synthesis, 2019
Proceedings of the 16th International Conference on Synthesis, 2019
Proceedings of the 16th International Conference on Synthesis, 2019
An IC Array for the Statistical Characterization of Time-Dependent Variability of Basic Circuit Blocks.
Proceedings of the 16th International Conference on Synthesis, 2019
A New Time Efficient Methodology for the Massive Characterization of RTN in CMOS Devices.
Proceedings of the IEEE International Reliability Physics Symposium, 2019
Generation of Lifetime-Aware Pareto-Optimal Fronts Using a Stochastic Reliability Simulator.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019
New method for the automated massive characterization of Bias Temperature Instability in CMOS transistors.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019
2018
A Comparison of Automated RF Circuit Design Methodologies: Online Versus Offline Passive Component Design.
IEEE Trans. Very Large Scale Integr. Syst., 2018
Enhanced systematic design of a voltage controlled oscillator using a two-step optimization methodology.
Integr., 2018
A novel design methodology for the mixed-domain optimization of a MEMS accelerometer.
Integr., 2018
Integr., 2018
Quasi-static PEEC planar solver using a weighted combination of 2D and 3D analytical Green's functions and a predictive meshing generator.
Integr., 2018
Proceedings of the 15th International Conference on Synthesis, 2018
Design Considerations of an SRAM Array for the Statistical Validation of Time-Dependent Variability Models.
Proceedings of the 15th International Conference on Synthesis, 2018
Proceedings of the 15th International Conference on Synthesis, 2018
Handling the Effects of Variability and Layout Parasitics in the Automatic Synthesis of LNAs.
Proceedings of the 15th International Conference on Synthesis, 2018
A Model Parameter Extraction Methodology Including Time-Dependent Variability for Circuit Reliability Simulation.
Proceedings of the 15th International Conference on Synthesis, 2018
Analysis of Body Bias and RTN-Induced Frequency Shift of Low Voltage Ring Oscillators in FDSOI Technology.
Proceedings of the 28th International Symposium on Power and Timing Modeling, 2018
Weighted time lag plot defect parameter extraction and GPU-based BTI modeling for BTI variability.
Proceedings of the IEEE International Reliability Physics Symposium, 2018
Proceedings of the 24th IEEE International Symposium on On-Line Testing And Robust System Design, 2018
2017
An Automated Design Methodology of RF Circuits by Using Pareto-Optimal Fronts of EM-Simulated Inductors.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2017
Radio-frequency inductor synthesis using evolutionary computation and Gaussian-process surrogate modeling.
Appl. Soft Comput., 2017
Proceedings of the 14th International Conference on Synthesis, 2017
Proceedings of the 14th International Conference on Synthesis, 2017
Proceedings of the 14th International Conference on Synthesis, 2017
Layout-aware challenges and a solution for the automatic synthesis of radio-frequency IC blocks.
Proceedings of the 14th International Conference on Synthesis, 2017
Proceedings of the 14th International Conference on Synthesis, 2017
New mapping strategies for pre-optimized inductor sets in bottom-up RF IC sizing optimization.
Proceedings of the 14th International Conference on Synthesis, 2017
A transistor array chip for the statistical characterization of process variability, RTN and BTI/CHC aging.
Proceedings of the 14th International Conference on Synthesis, 2017
Proceedings of the 14th International Conference on Synthesis, 2017
Proceedings of the 14th International Conference on Synthesis, 2017
Proceedings of the IEEE International Symposium on Circuits and Systems, 2017
An algorithm for a class of real-life multi-objective optimization problems with a sweeping objective.
Proceedings of the 2017 IEEE Congress on Evolutionary Computation, 2017
2016
Circuit Realization of the Synchronization of Two Chaotic Oscillators with Optimized Maximum Lyapunov Exponent.
Proceedings of the Advances in Chaos Theory and Intelligent Control, 2016
Integr., 2016
Comparison of QMC-based yield-aware pareto front techniques for multi-objective robust analog synthesis.
Integr., 2016
Proceedings of the 13th International Conference on Synthesis, 2016
Proceedings of the 13th International Conference on Synthesis, 2016
Proceedings of the 13th International Conference on Synthesis, 2016
Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016
2015
Proceedings of the IEEE 13th International New Circuits and Systems Conference, 2015
Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015
Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015
2014
Automated Design of Analog and High-frequency Circuits - A Computational Intelligence Approach
Studies in Computational Intelligence 501, Springer, ISBN: 978-3-642-39161-3, 2014
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2014
Implementation issues in the hierarchical composition of performance models of analog circuits.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014
2013
An Efficient Evolutionary Algorithm for Chance-Constrained Bi-Objective Stochastic Optimization.
IEEE Trans. Evol. Comput., 2013
Optimizing the positive Lyapunov exponent in multi-scroll chaotic oscillators with differential evolution algorithm.
Appl. Math. Comput., 2013
Proceedings of the Design, Automation and Test in Europe, 2013
2012
Self-adaptive lower confidence bound: A new general and effective prescreening method for Gaussian Process surrogate model assisted evolutionary algorithms.
Proceedings of the IEEE Congress on Evolutionary Computation, 2012
2011
Pathological Element-Based Active Device Models and Their Application to Symbolic Analysis.
IEEE Trans. Circuits Syst. I Regul. Pap., 2011
Efficient and Accurate Statistical Analog Yield Optimization and Variation-Aware Circuit Sizing Based on Computational Intelligence Techniques.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2011
Proceedings of the 20th European Conference on Circuit Theory and Design, 2011
Proceedings of the 20th European Conference on Circuit Theory and Design, 2011
Proceedings of the 20th European Conference on Circuit Theory and Design, 2011
2010
An accurate and efficient yield optimization method for analog circuits based on computing budget allocation and memetic search technique.
Proceedings of the Design, Automation and Test in Europe, 2010
Proceedings of the IEEE Congress on Evolutionary Computation, 2010
Stopping criteria in evolutionary algorithms for multi-objective performance optimization of integrated inductors.
Proceedings of the IEEE Congress on Evolutionary Computation, 2010
2009
A memetic approach to the automatic design of high-performance analog integrated circuits.
ACM Trans. Design Autom. Electr. Syst., 2009
Adaptive CMOS analog circuits for 4G mobile terminals - Review and state-of-the-art survey.
Microelectron. J., 2009
Integr., 2009
Applications of evolutionary computation techniques to analog, mixed-signal and RF circuit design - an overview.
Proceedings of the 16th IEEE International Conference on Electronics, 2009
Less expensive and high quality stopping criteria for MC-based analog IC yield optimization.
Proceedings of the 16th IEEE International Conference on Electronics, 2009
Proceedings of the 19th European Conference on Circuit Theory and Design, 2009
A fuzzy selection based constraint handling method for multi-objective optimization of analog cells.
Proceedings of the 19th European Conference on Circuit Theory and Design, 2009
Proceedings of the Design, Automation and Test in Europe, 2009
Fuzzy selection based differential evolution algorithm for analog cell sizing capturing imprecise human intentions.
Proceedings of the IEEE Congress on Evolutionary Computation, 2009
2008
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2008
Clock jitter error in multi-bit continuous-time sigma-delta modulators with non-return-to-zero feedback waveform.
Microelectron. J., 2008
Behavioral modeling, simulation and synthesis of multi-standard wireless receivers in MATLAB/SIMULINK.
Integr., 2008
2007
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007
2006
A New High-Level Synthesis Methodology of Cascaded Continuous-Time Sigma Delta Modulators.
IEEE Trans. Circuits Syst. II Express Briefs, 2006
Design of a 1.2-V 130nm CMOS 13-bit@40MS/s Cascade 2-2-1 Continuous-Time Sigma-Delta Modulator.
Proceedings of the IFIP VLSI-SoC 2006, 2006
Design of a 1.2-V cascade continuous-time Delta Sigma modulator for broadband telecommunications.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006
Reconfiguration of cascade Sigma Delta modulators for multistandard GSM/Bluetooth/UMTS/WLAN transceivers.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006
2005
High-level synthesis of switched-capacitor, switched-current and continuous-time ΣΔ modulators using SIMULINK-based time-domain behavioral models.
IEEE Trans. Circuits Syst. I Regul. Pap., 2005
Analysis of clock jitter error in multibit continuous-time ΣΔ modulators with NRZ feedback waveform.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005
2004
An optimization-based tool for the high-level synthesis of discrete-time and continuous-time ΣΔ modulators in the Matlab/Simulink environment.
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004
MATLAB/SIMULINK-Based High-Level Synthesis of Discrete-Time and Continuous-Time [Sigma, Delta] Modulators.
Proceedings of the 2004 Design, 2004
2003
Proceedings of the 2003 International Symposium on Circuits and Systems, 2003
Description Languages and Tools for the Behavioural Simulation of SD Modulators: a Comparative Survey.
Proceedings of the Forum on specification and Design Languages, 2003
Behavioural Modelling and Simulation of SigmaDelta Modulators Using Hardware Description Languages.
Proceedings of the 2003 Design, 2003
2001
Proceedings of the Conference on Design, Automation and Test in Europe, 2001
2000
Proceedings of the IEEE International Symposium on Circuits and Systems, 2000
Proceedings of the 2000 Design, 2000
A Hierarchical Approach for the Symbolic Analysis of Large Analog Integrated Circuits.
Proceedings of the 2000 Design, 2000
1999
RAPID-retargetability for reusability of application-driven quadrature D/A interface block design.
Proceedings of the 6th IEEE International Conference on Electronics, Circuits and Systems, 1999
Proceedings of the 1999 Design, 1999
1998
A simplification before and during generation methodology for symbolic large-circuit analysis.
Proceedings of the 5th IEEE International Conference on Electronics, Circuits and Systems, 1998
1997
An algorithm for numerical reference generation in symbolic analysis of large analog circuits.
Proceedings of the European Design and Test Conference, 1997
1995
Efficient symbolic computation of approximated small-signal characteristics of analog integrated circuits.
IEEE J. Solid State Circuits, March, 1995
Proceedings of the 1995 IEEE International Symposium on Circuits and Systems, ISCAS 1995, Seattle, Washington, USA, April 30, 1995
1994
Symbolic Analysis of Large Analog Integrated Circuits by Approximation During Expression Generation.
Proceedings of the 1994 IEEE International Symposium on Circuits and Systems, ISCAS 1994, London, England, UK, May 30, 1994
Proceedings of the 1994 IEEE International Symposium on Circuits and Systems, ISCAS 1994, London, England, UK, May 30, 1994
Proceedings of the 1994 IEEE/ACM International Conference on Computer-Aided Design, 1994
1992
Proceedings of the 1992 IEEE/ACM International Conference on Computer-Aided Design, 1992