Rafael Castro-López

Proceedings of the 19th International Conference on Synthesis, 2023

A Peak Detect & Hold circuit to measure and exploit RTN in a 65-nm CMOS PUF.

[BibT_eX]

[DOI]

Proceedings of the 19th International Conference on Synthesis, 2023

A Test Module for Aging Characterization of Digital Circuits.

[BibT_eX]

[DOI]

Jose M. Gata-Romero

Proceedings of the 19th International Conference on Synthesis, 2023

Reliability evaluation of IC Ring Oscillator PUFs.

[BibT_eX]

[DOI]

Proceedings of the 19th International Conference on Synthesis, 2023

Strategies for parameter extraction of the time constant distribution of time-dependent variability models for nanometer-scale devices.

[BibT_eX]

[DOI]

Proceedings of the 19th International Conference on Synthesis, 2023

Design considerations for a CMOS 65-nm RTN-based PUF.

[BibT_eX]

[DOI]

Proceedings of the 19th International Conference on Synthesis, 2023

Characterizing BTI and HCD in 1.2V 65nm CMOS Oscillators made from Combinational Standard Cells and Processor Logic Paths.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Reliability Physics Symposium, 2023

Challenges and solutions to the defect-centric modeling and circuit simulation of time-dependent variability.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Reliability Physics Symposium, 2023

2022

On the Impact of the Biasing History on the Characterization of Random Telegraph Noise.

[BibT_eX]

[DOI]

IEEE Trans. Instrum. Meas., 2022

A DRV-based bit selection method for SRAM PUF key generation and its impact on ECCs.

[BibT_eX]

[DOI]

Piedad Brox

Integr., 2022

A systematic approach to RTN parameter fitting based on the Maximum Current Fluctuation.

[BibT_eX]

[DOI]

Proceedings of the 18th International Conference on Synthesis, 2022

Impact of BTI and HCI on the reliability of a Majority Voter.

[BibT_eX]

[DOI]

Proceedings of the 18th International Conference on Synthesis, 2022

Characterization and analysis of BTI and HCI effects in CMOS current mirrors.

[BibT_eX]

[DOI]

Proceedings of the 18th International Conference on Synthesis, 2022

Machine Learning Approaches for Transformer Modeling.

[BibT_eX]

[DOI]

Proceedings of the 18th International Conference on Synthesis, 2022

On the use of an RTN simulator to explore the quality trade-offs of a novel RTN-based PUF.

[BibT_eX]

[DOI]

Eros Camacho-Ruiz

Proceedings of the 18th International Conference on Synthesis, 2022

High-level design of a novel PUF based on RTN.

[BibT_eX]

[DOI]

Eros Camacho-Ruiz

Proceedings of the 18th International Conference on Synthesis, 2022

A novel Physical Unclonable Function using RTN.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2022

A Smart SRAM-Cell Array for the Experimental Study of Variability Phenomena in CMOS Technologies.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Reliability Physics Symposium, 2022

2021

Hierarchical Yield-Aware Synthesis Methodology Covering Device-, Circuit-, and System-Level for Radiofrequency ICs.

[BibT_eX]

[DOI]

IEEE Access, 2021

2020

Flexible Setup for the Measurement of CMOS Time-Dependent Variability With Array-Based Integrated Circuits.

[BibT_eX]

[DOI]

José María López-Villegas

IEEE Trans. Instrum. Meas., 2020

A Multilevel Bottom-Up Optimization Methodology for the Automated Synthesis of RF Systems.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020

Synthesis of mm-Wave Wideband Receivers in 28-nm CMOS Technology for Automotive Radar Applications.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020

A robust and automated methodology for the analysis of Time-Dependent Variability at transistor level.

[BibT_eX]

[DOI]

Integr., 2020

Ready-to-Fabricate RF Circuit Synthesis Using a Layout- and Variability-Aware Optimization-Based Methodology.

[BibT_eX]

[DOI]

IEEE Access, 2020

Improving the reliability of SRAM-based PUFs in the presence of aging.

[BibT_eX]

[DOI]

Piedad Brox

Proceedings of the 15th Design & Technology of Integrated Systems in Nanoscale Era, 2020

2019

Two-Step RF IC Block Synthesis With Preoptimized Inductors and Full Layout Generation In-the-Loop.

[BibT_eX]

[DOI]

Nuno Horta

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2019

A two-step surrogate modeling strategy for single-objective and multi-objective optimization of radiofrequency circuits.

[BibT_eX]

[DOI]

Soft Comput., 2019

A Versatile CMOS Transistor Array IC for the Statistical Characterization of Time-Zero Variability, RTN, BTI, and HCI.

[BibT_eX]

[DOI]

IEEE J. Solid State Circuits, 2019

TiDeVa: A Toolbox for the Automated and Robust Analysis of Time-Dependent Variability at Transistor Level.

[BibT_eX]

[DOI]

Proceedings of the 16th International Conference on Synthesis, 2019

Synthesis of mm-Wave circuits using-EM-simulated passive structure libraries.

[BibT_eX]

[DOI]

Proceedings of the 16th International Conference on Synthesis, 2019

Experimental Characterization of Time-Dependent Variability in Ring Oscillators.

[BibT_eX]

[DOI]

Juan Núñez

Proceedings of the 16th International Conference on Synthesis, 2019

An IC Array for the Statistical Characterization of Time-Dependent Variability of Basic Circuit Blocks.

[BibT_eX]

[DOI]

Proceedings of the 16th International Conference on Synthesis, 2019

A New Time Efficient Methodology for the Massive Characterization of RTN in CMOS Devices.

[BibT_eX]

[DOI]

G. Pedreira

Proceedings of the IEEE International Reliability Physics Symposium, 2019

Generation of Lifetime-Aware Pareto-Optimal Fronts Using a Stochastic Reliability Simulator.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019

New method for the automated massive characterization of Bias Temperature Instability in CMOS transistors.

[BibT_eX]

[DOI]

Elisenda Roca Moreno

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019

2018

A Comparison of Automated RF Circuit Design Methodologies: Online Versus Offline Passive Component Design.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2018

Enhanced systematic design of a voltage controlled oscillator using a two-step optimization methodology.

[BibT_eX]

[DOI]

Integr., 2018

Lifetime Calculation Using a Stochastic Reliability Simulator for Analog ICs.

[BibT_eX]

[DOI]

Proceedings of the 15th International Conference on Synthesis, 2018

Design Considerations of an SRAM Array for the Statistical Validation of Time-Dependent Variability Models.

[BibT_eX]

[DOI]

Proceedings of the 15th International Conference on Synthesis, 2018

Automated Massive RTN Characterization Using a Transistor Array Chip.

[BibT_eX]

[DOI]

Proceedings of the 15th International Conference on Synthesis, 2018

Handling the Effects of Variability and Layout Parasitics in the Automatic Synthesis of LNAs.

[BibT_eX]

[DOI]

Proceedings of the 15th International Conference on Synthesis, 2018

A Model Parameter Extraction Methodology Including Time-Dependent Variability for Circuit Reliability Simulation.

[BibT_eX]

[DOI]

Proceedings of the 15th International Conference on Synthesis, 2018

Analysis of Body Bias and RTN-Induced Frequency Shift of Low Voltage Ring Oscillators in FDSOI Technology.

[BibT_eX]

[DOI]

Proceedings of the 28th International Symposium on Power and Timing Modeling, 2018

Weighted time lag plot defect parameter extraction and GPU-based BTI modeling for BTI variability.

[BibT_eX]

[DOI]

Victor M. van Santen

Hussam Amrouch

Jörg Henkel

Proceedings of the IEEE International Reliability Physics Symposium, 2018

CMOS Characterization and Compact Modelling for Circuit Reliability Simulation.

[BibT_eX]

[DOI]

Proceedings of the 24th IEEE International Symposium on On-Line Testing And Robust System Design, 2018

2017

An Automated Design Methodology of RF Circuits by Using Pareto-Optimal Fronts of EM-Simulated Inductors.

[BibT_eX]

[DOI]

José María López-Villegas

Javier J. Sieiro

Neus Vidal

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2017

An inductor modeling and optimization toolbox for RF circuit design.

[BibT_eX]

[DOI]

Integr., 2017

Radio-frequency inductor synthesis using evolutionary computation and Gaussian-process surrogate modeling.

[BibT_eX]

[DOI]

Appl. Soft Comput., 2017

Including a stochastic model of aging in a reliability simulation flow.

[BibT_eX]

[DOI]

Proceedings of the 14th International Conference on Synthesis, 2017

Systematic design of a voltage controlled oscillator using a layout-aware approach.

[BibT_eX]

[DOI]

Proceedings of the 14th International Conference on Synthesis, 2017

Layout-aware challenges and a solution for the automatic synthesis of radio-frequency IC blocks.

[BibT_eX]

[DOI]

Proceedings of the 14th International Conference on Synthesis, 2017

CASE: A reliability simulation tool for analog ICs.

[BibT_eX]

[DOI]

Proceedings of the 14th International Conference on Synthesis, 2017

New mapping strategies for pre-optimized inductor sets in bottom-up RF IC sizing optimization.

[BibT_eX]

[DOI]

Proceedings of the 14th International Conference on Synthesis, 2017

A transistor array chip for the statistical characterization of process variability, RTN and BTI/CHC aging.

[BibT_eX]

[DOI]

Enrique Barajas

Xavier Aragonès

Diego Mateo

Proceedings of the 14th International Conference on Synthesis, 2017

TARS: A toolbox for statistical reliability modeling of CMOS devices.

[BibT_eX]

[DOI]

Proceedings of the 14th International Conference on Synthesis, 2017

A size-adaptive time-step algorithm for accurate simulation of aging in analog ICs.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2017

An algorithm for a class of real-life multi-objective optimization problems with a sweeping objective.

[BibT_eX]

[DOI]

Proceedings of the 2017 IEEE Congress on Evolutionary Computation, 2017

2016

Reliability simulation for analog ICs: Goals, solutions, and challenges.

[BibT_eX]

[DOI]

Integr., 2016

Frequency-dependent parameterized macromodeling of integrated inductors.

[BibT_eX]

[DOI]

Y. Ye

Domenico Spina

Tom Dhaene

Proceedings of the 13th International Conference on Synthesis, 2016

SIDe-O: A toolbox for surrogate inductor design and optimization.

[BibT_eX]

[DOI]

Proceedings of the 13th International Conference on Synthesis, 2016

High-level optimization of ΣΔ modulators using multi-objetive evolutionary algorithms.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2016

Live demonstration: High-level optimization of ΣΔ modulators using multi-objetive evolutionary algorithms.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2016

Accurate synthesis of integrated RF passive components using surrogate models.

[BibT_eX]

[DOI]

Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016

2015

Design space exploration using hierarchical composition of performance models.

[BibT_eX]

[DOI]

Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015

Physical vs. surrogate models of passive RF devices.

[BibT_eX]

[DOI]

Mouna Kotti

Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015

2014

Automated Generation of the Optimal Performance Trade-Offs of Integrated Inductors.

[BibT_eX]

[DOI]

José María López-Villegas

Javier J. Sieiro

Neus Vidal

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2014

Implementation issues in the hierarchical composition of performance models of analog circuits.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014

2011

Layout-aware Pareto fronts of electronic circuits.

[BibT_eX]

[DOI]

Proceedings of the 20th European Conference on Circuit Theory and Design, 2011

2010

A 0.13 µm CMOS adaptive sigma-delta modulator for triple-mode GSM/Bluetooth/UMTS applications.

[BibT_eX]

[DOI]

Alonso Morgado

Rocío del Río Fernández

Maria Belen Pérez-Verdú

Microelectron. J., 2010

Stopping criteria in evolutionary algorithms for multi-objective performance optimization of integrated inductors.

[BibT_eX]

[DOI]

Juan Esteban-Muller

Proceedings of the IEEE Congress on Evolutionary Computation, 2010

2009

A memetic approach to the automatic design of high-performance analog integrated circuits.

[BibT_eX]

[DOI]

Bo Liu

Georges G. E. Gielen

ACM Trans. Design Autom. Electr. Syst., 2009

Adaptive CMOS analog circuits for 4G mobile terminals - Review and state-of-the-art survey.

[BibT_eX]

[DOI]

Alonso Morgado

Edwin C. Becerra-Alvarez

Rocío del Río

Maria Belen Pérez-Verdú

Microelectron. J., 2009

AMS/RF-CMOS circuit design for wireless transceivers.

[BibT_eX]

[DOI]

Delia Rodríguez de Llera

Mohammed Ismail

Integr., 2009

Applications of evolutionary computation techniques to analog, mixed-signal and RF circuit design - an overview.

[BibT_eX]

[DOI]

Mourad Fakhfakh

Proceedings of the 16th IEEE International Conference on Electronics, 2009

Hierarchical synthesis based on pareto-optimal fronts.

[BibT_eX]

[DOI]

Proceedings of the 19th European Conference on Circuit Theory and Design, 2009

Analog layout synthesis - Recent advances in topological approaches.

[BibT_eX]

[DOI]

Mark Po-Hung Lin

Martin Strasser

Proceedings of the Design, Automation and Test in Europe, 2009

2008

An Integrated Layout-Synthesis Approach for Analog ICs.

[BibT_eX]

[DOI]

Oscar Guerra

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2008

Behavioral modeling, simulation and synthesis of multi-standard wireless receivers in MATLAB/SIMULINK.

[BibT_eX]

[DOI]

Juan Francisco Fernández-Bootello

Integr., 2008

2006

A 12-bit CMOS Current Steering D/A Converter for Embedded Systems.

[BibT_eX]

[DOI]

Jesús Ruiz-Amaya

Manuel Delgado-Restituto

Davide Brandano

Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems 2006, 2006

2003

Accurate VHDL-based simulation of Sigma-Delta modulators.

[BibT_eX]

[DOI]

Fernando Medeiro

Proceedings of the 2003 International Symposium on Circuits and Systems, 2003

Description Languages and Tools for the Behavioural Simulation of SD Modulators: a Comparative Survey.

[BibT_eX]

[DOI]

Proceedings of the Forum on specification and Design Languages, 2003

A 1000FPS@128×128 vision processor with 8-bit digitized I/O.

[BibT_eX]

[DOI]

Gustavo Liñán Cembrano

Servando Espejo-Meana

Proceedings of the ESSCIRC 2003, 2003

Behavioural Modelling and Simulation of SigmaDelta Modulators Using Hardware Description Languages.

[BibT_eX]

[DOI]

Fernando Medeiro

Proceedings of the 2003 Design, 2003

2001

Retargeting of mixed-signal blocks for SoCs.

[BibT_eX]

[DOI]

Manuel Delgado-Restituto

Proceedings of the Conference on Design, Automation and Test in Europe, 2001

1999

RAPID-retargetability for reusability of application-driven quadrature D/A interface block design.

[BibT_eX]

[DOI]

Manuel Delgado-Restituto