Josef Strnadel
Orcid: 0000-0001-6327-5990
According to our database1,
Josef Strnadel
authored at least 32 papers
between 2002 and 2022.
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Bibliography
2022
Proceedings of the 25th International Symposium on Design and Diagnostics of Electronic Circuits and Systems, 2022
2021
Using Model Checker to Analyze and Test Digital Circuits with Regard to Delay Faults.
Proceedings of the 24th International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2021
2020
Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020
2019
Using Statistical Model Checking to Assess Reliability for Bathtub-Shaped Failure Rates.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019
2018
IEEE Des. Test, 2018
Proceedings of the Leveraging Applications of Formal Methods, Verification and Validation. Verification, 2018
2017
On Dependability Assessment of Fault Tolerant Systems by Means of Statistical Model Checking.
Proceedings of the Euromicro Conference on Digital System Design, 2017
2016
On Creation and Analysis of Reliability Models by Means of Stochastic Timed Automata and Statistical Model Checking: Principle.
Proceedings of the Leveraging Applications of Formal Methods, Verification and Validation: Foundational Techniques, 2016
2015
Comparison of Generally Applicable Mechanisms for Preventing Embedded Event-Driven Real-Time Systems from Interrupt Overloads.
Proceedings of the 2015 4th Eastern European Regional Conference on the Engineering of Computer Based Systems, 2015
2014
Comput. Informatics, 2014
Comparing Availability-Aware Real-Time Schedulers by Means of Configurable Experimental Framework.
Proceedings of the 17th Euromicro Conference on Digital System Design, 2014
2013
On design of priority-driven load-adaptive monitoring-based hardware for managing interrupts in embedded event-triggered real-time systems.
Proceedings of the 16th IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2013
Load-Adaptive Monitor-Driven Hardware for Preventing Embedded Real-Time Systems from Overloads Caused by Excessive Interrupt Rates.
Proceedings of the Architecture of Computing Systems - ARCS 2013, 2013
2012
On Distribution and Impact of Fault Effects at Real-Time Kernel and Application Levels.
Proceedings of the 15th Euromicro Conference on Digital System Design, 2012
Monitoring-driven HW/SW interrupt overload prevention for embedded real-time systems.
Proceedings of the IEEE 15th International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2012
2011
On RTL Testability and Gate-Level Stuck-At-Fault Coverage Correlation for Scan Circuits.
Proceedings of the 14th Euromicro Conference on Digital System Design, 2011
2010
Proceedings of the Evolvable Systems: From Biology to Hardware, 2010
The Use of Genetic Algorithm to Derive Correlation Between Test Vector and Scan Register Sequences and Reduce Power Consumption.
Proceedings of the 13th Euromicro Conference on Digital System Design, 2010
Reduction of power dissipation through parallel optimization of test vector and scan register sequences.
Proceedings of the 13th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems, 2010
2008
Comput. Informatics, 2008
Proceedings of the 11th Euromicro Conference on Digital System Design: Architectures, 2008
2007
Proceedings of the Tenth Euromicro Conference on Digital System Design: Architectures, 2007
2006
Comput. Artif. Intell., 2006
SET: Interactive Tool for Learning and Training Scan-Based DFT Principles and Their Consequences to Parameters of Embedded System.
Proceedings of the 13th Annual IEEE International Conference and Workshop on Engineering of Computer Based Systems (ECBS 2006), 2006
Novel Optimizing Approach in the Area of STEP-Based Construction of Sessionless, Power-Constrainted, TAM and Time Optimal Test Schedules.
Proceedings of the 13th Annual IEEE International Conference and Workshop on Engineering of Computer Based Systems (ECBS 2006), 2006
Proceedings of the Ninth Euromicro Conference on Digital System Design: Architectures, Methods and Tools (DSD 2006), 30 August, 2006
Power-Constrained, Sessionless SoC Test Scheduling Based on Exploration of I-Schedule State-Space.
Proceedings of the 9th IEEE Workshop on Design & Diagnostics of Electronic Circuits & Systems (DDECS 2006), 2006
2005
Automatic Discovery of RTL Benchmark Circuits with Predefined Testability Properties.
Proceedings of the 2005 NASA / DoD Conference on Evolvable Hardware (EH 2005), 29 June, 2005
Educational Tool for the Demonstration of DfT Principles Based on Scan Methodologies.
Proceedings of the Eighth Euromicro Symposium on Digital Systems Design (DSD 2005), 30 August, 2005
2004
The Identification of registers in RTL Structures for the Test Application.
Proceedings of the International Symposium on Leveraging Applications of Formal Methods, 2004
2003
Proceedings of the 2003 Euromicro Symposium on Digital Systems Design (DSD 2003), 2003
2002
Testability Improvements Based on the Combination of Analytical and Evolutionary Approaches at RT Level.
Proceedings of the 2002 Euromicro Symposium on Digital Systems Design (DSD 2002), 2002