Juan Pablo Duarte

According to our database, Juan Pablo Duarte authored at least 5 papers between 2013 and 2016.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2016

Thermal resistance modeling in FDSOI transistors with industry standard model BSIM-IMG.

Pragya Kushwaha, K. Bala Krishna, Harshit Agarwal, Sourabh Khandelwal, Juan Pablo Duarte, Chenming Hu, Yogesh Singh Chauhan

Microelectron. J., 2016

2015

Modeling STI Edge Parasitic Current for Accurate Circuit Simulations.

Sourabh Khandelwal, Harshit Agarwal, Juan Pablo Duarte, Kaiman Chan, Sagnik Dey, Yogesh Singh Chauhan, Chenming Hu

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2015

BSIM-CMG: Standard FinFET compact model for advanced circuit design.

Juan Pablo Duarte, Sourabh Khandelwal, Aditya Sankar Medury, Chenming Hu, Pragya Kushwaha, Harshit Agarwal, Avirup Dasgupta, Yogesh Singh Chauhan

Proceedings of the ESSCIRC Conference 2015, 2015

2013

BSIM - SPICE Models Enable FinFET and UTB IC Designs.

Navid Paydavosi, Sriramkumar Venugopalan, Yogesh Singh Chauhan, Juan Pablo Duarte, Srivatsava Jandhyala, Ali M. Niknejad, Chenming Hu

IEEE Access, 2013

BSIM compact MOSFET models for SPICE simulation.

Yogesh Singh Chauhan, Sriramkumar Venugopalan, Navid Paydavosi, Pragya Kushwaha, Srivatsava Jandhyala, Juan Pablo Duarte, Shantanu Agnihotri, Chandan Yadav, Harshit Agarwal, Ali M. Niknejad, Chenming Calvin Hu

Proceedings of the 20th International Conference Mixed Design of Integrated Circuits and Systems, 2013