Chenming Hu
Orcid: 0009-0000-9599-3401
According to our database1,
Chenming Hu authored at least 83 papers
between 1989 and 2026.
Collaborative distances:
Collaborative distances:
Awards
IEEE Fellow
IEEE Fellow 1990, "For contributions to the understanding of hot-electron effects in MOS devices.".
Timeline
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Book In proceedings Article PhD thesis Dataset OtherLinks
Online presence:
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on zbmath.org
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on id.loc.gov
On csauthors.net:
Bibliography
2026
Spike-EVPR: Deep Spiking Residual Networks With SNN-Tailored Representations for Event-Based Visual Place Recognition.
IEEE Robotics Autom. Lett., June, 2026
2025
Physics-Informed Neural Networks for Device and Circuit Modeling: A Case Study of NeuroSPICE.
CoRR, December, 2025
EDE-Distill: Boosting Event-Based Monocular Depth Estimation Performance via Knowledge Distillation.
IEEE Robotics Autom. Lett., August, 2025
Fully Asynchronous Neuromorphic Perception for Mobile Robot Dodging With Loihi Chips.
IEEE Trans Autom. Sci. Eng., 2025
Orchard variable rate spraying method and experimental study based on multidimensional prescription maps.
Comput. Electron. Agric., 2025
Proceedings of the Thirteenth International Conference on Learning Representations, 2025
2024
EV-MGRFlowNet: Motion-Guided Recurrent Network for Unsupervised Event-Based Optical Flow With Hybrid Motion-Compensation Loss.
IEEE Trans. Instrum. Meas., 2024
Spike-EVPR: Deep Spiking Residual Network with Cross-Representation Aggregation for Event-Based Visual Place Recognition.
CoRR, 2024
3DIC with Stacked FinFET, Inter-Level Metal, and Field-Size (25×33mm<sup>2</sup>) Single-Crystalline Si on SiO2 by Elevated-Epi.
Proceedings of the IEEE Symposium on VLSI Technology and Circuits 2024, 2024
2023
Planning the temporary takeoff/landing site's location for a pesticide spraying helicopter based on an intelligent fusion algorithm.
Comput. Electron. Agric., June, 2023
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2023
Record Transconductance in Leff~30 nm Self-Aligned Replacement Gate ETSOI nFETs Using Low EOT Negative Capacitance HfO2-ZrO2 Superlattice Gate Stack.
Proceedings of the 2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), 2023
2022
On the PBTI Reliability of Low EOT Negative Capacitance 1.8 nm HfO2-ZrO2 Superlattice Gate Stack on Lg=90 nm nFETs.
Proceedings of the IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits 2022), 2022
Artificial Neural Network Surrogate Models for Efficient Design Space Exploration of 14-nm FinFETs.
Proceedings of the Device Research Conference, 2022
Proceedings of the Device Research Conference, 2022
2021
J. Vis. Commun. Image Represent., 2021
2020
Image Vis. Comput., 2020
Investigation of a preliminary ventilation energy-recovery system for poultry houses.
Comput. Electron. Agric., 2020
Proceedings of the 2020 Device Research Conference, 2020
2019
Comput. Electron. Agric., 2019
Computational Fluid Dynamics aided investigation and optimization of a tunnel-ventilated poultry house in China.
Comput. Electron. Agric., 2019
Proceedings of the IEEE Custom Integrated Circuits Conference, 2019
2017
Proceedings of the 30th International Conference on VLSI Design and 16th International Conference on Embedded Systems, 2017
Proceedings of the 2017 IEEE/ACM International Symposium on Low Power Electronics and Design, 2017
2016
Thermal resistance modeling in FDSOI transistors with industry standard model BSIM-IMG.
Microelectron. J., 2016
2015
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2015
Proceedings of the ESSCIRC Conference 2015, 2015
2013
Proceedings of the 20th International Conference Mixed Design of Integrated Circuits and Systems, 2013
Proceedings of the European Solid-State Device Research Conference, 2013
2012
Proceedings of the 38th European Solid-State Circuit conference, 2012
Proceedings of the 38th European Solid-State Circuit conference, 2012
Proceedings of the IEEE 2012 Custom Integrated Circuits Conference, 2012
2011
Proceedings of the 48th Design Automation Conference, 2011
International Series on Advances in Solid State Electronics and Technology, World Scientific, ISBN: 978-981-4390-96-5, 2011
2010
2005
Impact of on-chip interconnect frequency-dependent R(f)L(f) on digital and RF design.
IEEE Trans. Very Large Scale Integr. Syst., 2005
Proceedings of the 6th International Symposium on Quality of Electronic Design (ISQED 2005), 2005
2004
A Non-Charge-Sheet Based Analytical Model of Undoped Symmetric Double-Gate MOSFETs Using SPP Approach.
Proceedings of the 5th International Symposium on Quality of Electronic Design (ISQED 2004), 2004
Proceedings of the IEEE 2004 Custom Integrated Circuits Conference, 2004
2003
Improved a priori interconnect predictions and technology extrapolation in the GTX system.
IEEE Trans. Very Large Scale Integr. Syst., 2003
Bidirectional closed-form transformation between on-chip coupling noise waveforms and interconnect delay-change curves.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2003
Microelectron. Reliab., 2003
Loop-based interconnect modeling and optimization approach for multigigahertz clock network design.
IEEE J. Solid State Circuits, 2003
A scaleable model for STI mechanical stress effect on layout dependence of MOS electrical characteristics.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2003
A unified model for partial-depletion and full-depletion SOI circuit designs: using BSIMPD as a foundation.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2003
2002
Effective on-chip inductance modeling for multiple signal lines and application to repeater insertion.
IEEE Trans. Very Large Scale Integr. Syst., 2002
Impact of spatial intrachip gate length variability on theperformance of high-speed digital circuits.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2002
Proceedings of the 7th Asia and South Pacific Design Automation Conference (ASP-DAC 2002), 2002
Studying the Impact of Gate Tunneling on Dynamic Behaviors of Partially-Depleted SOI CMOS Using BSIMPD.
Proceedings of the 3rd International Symposium on Quality of Electronic Design, 2002
Proceedings of the IEEE 2002 Custom Integrated Circuits Conference, 2002
2001
Accurate in situ measurement of peak noise and delay change induced by interconnect coupling.
IEEE J. Solid State Circuits, 2001
IEEE J. Solid State Circuits, 2001
Effective On-chip Inductance Modeling for Multiple Signal Lines and Application on Repeater Insertion.
Proceedings of the 2nd International Symposium on Quality of Electronic Design (ISQED 2001), 2001
Methodology of self-heating free parameter extraction and circuit simulation for SOI CMOS.
Proceedings of the IEEE 2001 Custom Integrated Circuits Conference, 2001
2000
IEEE J. Solid State Circuits, 2000
Impact of Systematic Spatial Intra-Chip Gate Length Variability on Performance of High-Speed Digital Circuits.
Proceedings of the 2000 IEEE/ACM International Conference on Computer-Aided Design, 2000
Effects of Global Interconnect Optimizations on Performance Estimation of Deep Submicron Design.
Proceedings of the 2000 IEEE/ACM International Conference on Computer-Aided Design, 2000
Proceedings of the IEEE 2000 Custom Integrated Circuits Conference, 2000
New paradigm of predictive MOSFET and interconnect modeling for early circuit simulation.
Proceedings of the IEEE 2000 Custom Integrated Circuits Conference, 2000
1999
Dynamic threshold pass-transistor logic for improved delay at lower power supply voltages.
IEEE J. Solid State Circuits, 1999
Performance and reliability comparison between asymmetric and symmetric LDD devices and logic gates.
IEEE J. Solid State Circuits, 1999
Proceedings of the 36th Conference on Design Automation, 1999
1998
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1998
Investigation of interconnect capacitance characterization using charge-based capacitance measurement (CBCM) technique and three-dimensional simulation.
IEEE J. Solid State Circuits, 1998
IEEE J. Solid State Circuits, 1998
Proceedings of the 35th Conference on Design Automation, 1998
Proceedings of the IEEE 1998 Custom Integrated Circuits Conference, 1998
Proceedings of the IEEE 1998 Custom Integrated Circuits Conference, 1998
1997
Proceedings of the 1997 International Symposium on Low Power Electronics and Design, 1997
1996
Device design for low power electronics with accurate deep submicrometer LDD-MOSFET models.
Proceedings of the 1996 International Symposium on Low Power Electronics and Design, 1996
1994
IEEE J. Solid State Circuits, March, 1994
1993
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1993
1992
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1992
1991
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1991
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1991
1989
Proceedings of the Computer Design: VLSI in Computers and Processors, 1989