Jude Haris

According to our database, Jude Haris authored at least 11 papers between 2021 and 2026.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2026

PoTAcc: A Pipeline for End-to-End Acceleration of Power-of-Two Quantized DNNs.

Rappy Saha, Jude Haris, Nicolas Bohm Agostini, David R. Kaeli, José Cano

CoRR, May, 2026

LLM-Driven Design Space Exploration of FPGA-based Accelerators.

Vinamra Sharma, Xingjian Fu, Jude Haris, José Cano

CoRR, May, 2026

Multi-Partner Project: dAIEDGE - A Network of Excellence for Distributed, Trustworthy, Efficient and Scalable AI at the Edge.

Alain Pagani, José Cano, Haralampos-G. Stratigopoulos, Aysajan Abidin, Mhd Rashed Al Koutayni, Luca Benini, Angelos Bilas, Alessandro Capotondi, Roberto Cavicchioli, Brian Clerkin, Oscar Déniz-Suárez, Margaux Divernois, Baptiste Dupertuis, Dorvan Favre, Giulio Gambardella, Ander García Gangoiti, Carlo Augusto Grazia, Dominik Günzel, Jude Haris, Klodjan K. Hidri, Maïck Huguenin, Manal Jammal, Paul Kling, Christos Kozanitis, Xavier Lessage, Srikanth Mandapati, Philippe Massonet, Alfio Di Mauro, Varesh Mishra, Juan Odriozola, Javier Parra-Domínguez, Nuria Pazos, Viviane Potocnik, Miguel de Prado, Rohit Prasad, Spyridon Raptis, Gregoire Rebstein, Ignacio Sañudo Olmedo, Mohamed Selim, Chinmay Satish Shrivastav, Noelia Vállez, Giorgos Vasiliadis, Micaela Verrucchi, Enrico Vincenzi, Damian Vizár, Devendra Vyas, Stefan Wiehle

Proceedings of the Design, Automation & Test in Europe Conference, 2026

2025

F-BFQ: Flexible Block Floating-Point Quantization Accelerator for LLMs.

Jude Haris, José Cano

CoRR, October, 2025

Accelerating Transposed Convolutions on FPGA-Based Edge Devices.

Jude Haris, José Cano

Proceedings of the 35th International Conference on Field-Programmable Logic and Applications, 2025

2024

Accelerating PoT Quantization on Edge Devices.

Rappy Saha, Jude Haris, José Cano

CoRR, 2024

Designing Efficient LLM Accelerators for Edge Devices.

Jude Haris, Rappy Saha, Wenhao Hu, José Cano

CoRR, 2024

Data Transfer Optimizations for Host-CPU and Accelerators in AXI4MLIR.

Jude Haris, Nicolas Bohm Agostini, Antonino Tumeo, David R. Kaeli, José Cano

CoRR, 2024

AXI4MLIR: User-Driven Automatic Host Code Generation for Custom AXI-Based Accelerators.

Nicolas Bohm Agostini, Jude Haris, Perry Gibson, Malith Jayaweera, Norm Rubin, Antonino Tumeo, José L. Abellán, José Cano, David R. Kaeli

Proceedings of the IEEE/ACM International Symposium on Code Generation and Optimization, 2024

2023

SECDA-TFLite: A toolkit for efficient development of FPGA-based DNN accelerators for edge inference.

Jude Haris, Perry Gibson, José Cano, Nicolas Bohm Agostini, David R. Kaeli

J. Parallel Distributed Comput., March, 2023

2021

SECDA: Efficient Hardware/Software Co-Design of FPGA-based DNN Accelerators for Edge Inference.

Jude Haris, Perry Gibson, José Cano, Nicolas Bohm Agostini, David R. Kaeli

Proceedings of the 33rd IEEE International Symposium on Computer Architecture and High Performance Computing, 2021