Alessandro Capotondi

Orcid: 0000-0001-8705-0761

According to our database1, Alessandro Capotondi authored at least 39 papers between 2013 and 2024.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Dataset
Other 

Links

Online presence:

On csauthors.net:

Bibliography

2024
ShareBERT: Embeddings Are Capable of Learning Hidden Layers.
Proceedings of the Thirty-Eighth AAAI Conference on Artificial Intelligence, 2024

2023
The Importance of Worst-Case Memory Contention Analysis for Heterogeneous SoCs.
CoRR, 2023

Heterogeneous Encoders Scaling in the Transformer for Neural Machine Translation.
Proceedings of the Seventh Workshop on Natural Language for Artificial Intelligence (NL4AI 2023) co-located with 22th International Conference of the Italian Association for Artificial Intelligence (AIxIA 2023), 2023

A Request for Clarity over the End of Sequence Token in the Self-Critical Sequence Training.
Proceedings of the Image Analysis and Processing - ICIAP 2023, 2023

HULK-V: a Heterogeneous Ultra-low-power Linux capable RISC-V SoC.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2023

Fine-Grained QoS Control via Tightly-Coupled Bandwidth Monitoring and Regulation for FPGA-based Heterogeneous SoCs.
Proceedings of the 60th ACM/IEEE Design Automation Conference, 2023

Exploiting Multiple Sequence Lengths in Fast End to End Training for Image Captioning.
Proceedings of the IEEE International Conference on Big Data, 2023

2022
ExpansionNet v2: Block Static Expansion in fast end to end training for Image Captioning.
CoRR, 2022

Understanding and Mitigating Memory Interference in FPGA-based HeSoCs.
Proceedings of the 2022 Design, Automation & Test in Europe Conference & Exhibition, 2022

An FPGA Overlay for Efficient Real-Time Localization in 1/10th Scale Autonomous Vehicles.
Proceedings of the 2022 Design, Automation & Test in Europe Conference & Exhibition, 2022

2021
Robustifying the Deployment of tinyML Models for Autonomous Mini-Vehicles.
Sensors, 2021

A TinyML Platform for On-Device Continual Learning With Quantized Latent Replays.
IEEE J. Emerg. Sel. Topics Circuits Syst., 2021

Robustifying the Deployment of tinyML Models for Autonomous Mini-Vehicles.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2021

Unmanned Vehicles in Smart Farming: a Survey and a Glance at Future Horizons.
Proceedings of the DroneSE and RAPIDO '21: Methods and Tools, 2021

A RISC-V-based FPGA Overlay to Simplify Embedded Accelerator Deployment.
Proceedings of the 24th Euromicro Conference on Digital System Design, 2021

2020
CMix-NN: Mixed Low-Precision CNN Library for Memory-Constrained Edge Devices.
IEEE Trans. Circuits Syst. II Express Briefs, 2020

Exploring NEURAghe: A Customizable Template for APSoC-Based CNN Inference at the Edge.
IEEE Embed. Syst. Lett., 2020

Robust navigation with tinyML for autonomous mini-vehicles.
CoRR, 2020

Memory-Latency-Accuracy Trade-Offs for Continual Learning on a RISC-V Extreme-Edge Node.
Proceedings of the IEEE Workshop on Signal Processing Systems, 2020

Leveraging Automated Mixed-Low-Precision Quantization for Tiny Edge Microcontrollers.
Proceedings of the IoT Streams for Data-Driven Predictive Maintenance and IoT, Edge, and Mobile for Embedded Machine Learning, 2020

Memory-Driven Mixed Low Precision Quantization for Enabling Deep Network Inference on Microcontrollers.
Proceedings of Machine Learning and Systems 2020, 2020

A Systematic Assessment of Embedded Neural Networks for Object Detection.
Proceedings of the 25th IEEE International Conference on Emerging Technologies and Factory Automation, 2020

Mixed-data-model heterogeneous compilation and OpenMP offloading.
Proceedings of the CC '20: 29th International Conference on Compiler Construction, 2020

2018
NEURAghe: Exploiting CPU-FPGA Synergies for Efficient and Flexible CNN Inference Acceleration on Zynq SoCs.
ACM Trans. Reconfigurable Technol. Syst., 2018

The Quest for Energy-Efficient I$ Design in Ultra-Low-Power Clustered Many-Cores.
IEEE Trans. Multi Scale Comput. Syst., 2018

Runtime Support for Multiple Offload-Based Programming Models on Clustered Manycore Accelerators.
IEEE Trans. Emerg. Top. Comput., 2018

Quantized NNs as the definitive solution for inference on low-power ARM MCUs?: work-in-progress.
Proceedings of the International Conference on Hardware/Software Codesign and System Synthesis, 2018

HERO: an open-source research platform for HW/SW exploration of heterogeneous manycore systems.
Proceedings of the 2nd Workshop on AutotuniNg and aDaptivity AppRoaches for Energy efficient HPC Systems, 2018

2017
HERO: Heterogeneous Embedded Research Platform for Exploring RISC-V Manycore Accelerators on FPGA.
CoRR, 2017

Enabling zero-copy OpenMP offloading on the PULP many-core accelerator.
Proceedings of the 20th International Workshop on Software and Compilers for Embedded Systems, 2017

2016
Programming models and tools for many-core platforms ; Modelli e strumenti di programmazione parallela per piattaforme many-core.
PhD thesis, 2016

Controlling NUMA effects in embedded manycore applications with lightweight nested parallelism support.
Parallel Comput., 2016

On the effectiveness of OpenMP teams for cluster-based many-core accelerators.
Proceedings of the International Conference on High Performance Computing & Simulation, 2016

2015
Simplifying Many-Core-Based Heterogeneous SoC Programming With Offload Directives.
IEEE Trans. Ind. Informatics, 2015

Enabling Scalable and Fine-Grained Nested Parallelism on Embedded Many-cores.
Proceedings of the IEEE 9th International Symposium on Embedded Multicore/Many-core Systems-on-Chip, 2015

PULP: A parallel ultra low power platform for next generation IoT applications.
Proceedings of the 2015 IEEE Hot Chips 27 Symposium (HCS), 2015

Runtime Support for Multiple Offload-Based Programming Models on Embedded Manycore Accelerators.
Proceedings of the 2015 International Workshop on Code Optimisation for Multi and Many Cores, 2015

2014
Augmenting manycore programmable accelerators with photonic interconnect technology for the high-end embedded computing domain.
Proceedings of the Eighth IEEE/ACM International Symposium on Networks-on-Chip, 2014

2013
Improving the programmability of STHORM-based heterogeneous systems with offload-enabled OpenMP.
Proceedings of the 1st International Workshop on Many-core Embedded Systems 2013, 2013


  Loading...