Giulio Gambardella

Orcid: 0000-0001-6183-5077

According to our database1, Giulio Gambardella authored at least 35 papers between 2011 and 2023.

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Bibliography

2023
On the RTL Implementation of FINN Matrix Vector Unit.
ACM Trans. Embed. Comput. Syst., November, 2023

Fault-Tolerant Neural Network Accelerators With Selective TMR.
IEEE Des. Test, April, 2023

2022
On the RTL Implementation of FINN Matrix Vector Compute Unit.
CoRR, 2022

2021
Evaluation of Optimized CNNs on Heterogeneous Accelerators Using a Novel Benchmarking Approach.
IEEE Trans. Computers, 2021

2020
FAT: Training Neural Networks for Reliable Inference Under Hardware Faults.
Proceedings of the IEEE International Test Conference, 2020

Evaluation of Optimized CNNs on FPGA and non-FPGA based Accelerators using a Novel Benchmarking Approach.
Proceedings of the FPGA '20: The 2020 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2020

2019
Synetgy: Algorithm-hardware Co-design for ConvNet Accelerators on Embedded FPGAs.
Proceedings of the 2019 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2019

Efficient Error-Tolerant Quantized Neural Network Accelerators.
Proceedings of the 2019 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2019

2018
FINN-<i>R</i>: An End-to-End Deep-Learning Framework for Fast Exploration of Quantized Neural Networks.
ACM Trans. Reconfigurable Technol. Syst., 2018

FINN-R: An End-to-End Deep-Learning Framework for Fast Exploration of Quantized Neural Networks.
CoRR, 2018

FINN-L: Library Extensions and Design Trade-Off Analysis for Variable Precision LSTM Networks on FPGAs.
Proceedings of the 28th International Conference on Field Programmable Logic and Applications, 2018

Customizing Low-Precision Deep Neural Networks for FPGAs.
Proceedings of the 28th International Conference on Field Programmable Logic and Applications, 2018

Inference of quantized neural networks on heterogeneous all-programmable devices.
Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018

Accuracy to Throughput Trade-Offs for Reduced Precision Neural Networks on Reconfigurable Logic.
Proceedings of the Applied Reconfigurable Computing. Architectures, Tools, and Applications, 2018

2017
Compressing Low Precision Deep Neural Networks Using Sparsity-Induced Regularization in Ternary Networks.
Proceedings of the Neural Information Processing - 24th International Conference, 2017

Scaling Neural Network Performance through Customized Hardware Architectures on Reconfigurable Logic.
Proceedings of the 2017 IEEE International Conference on Computer Design, 2017

Scaling Binarized Neural Networks on Reconfigurable Logic.
Proceedings of the 8th Workshop and 6th Workshop on Parallel Programming and Run-Time Management Techniques for Many-core Architectures and Design Tools and Architectures for Multicore Embedded Computing Platforms, 2017

FINN: A Framework for Fast, Scalable Binarized Neural Network Inference.
Proceedings of the 2017 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2017

2015
SA-FEMIP: A Self-Adaptive Features Extractor and Matcher IP-Core Based on Partially Reconfigurable FPGAs for Space Applications.
IEEE Trans. Very Large Scale Integr. Syst., 2015

SATTA: A Self-Adaptive Temperature-Based TDF Awareness Methodology for Dynamically Reconfigurable FPGAs.
ACM Trans. Reconfigurable Technol. Syst., 2015

2014
Dynamic partial reconfiguration for dependable systems.
PhD thesis, 2014

A cloud-based Cyber-Physical System for environmental monitoring.
Proceedings of the 3rd Mediterranean Conference on Embedded Computing, 2014

A novel methodology to increase fault tolerance in autonomous FPGA-based systems.
Proceedings of the 2014 IEEE 20th International On-Line Testing Symposium, 2014

On Enhancing Fault Injection's Capabilities and Performances for Safety Critical Systems.
Proceedings of the 17th Euromicro Conference on Digital System Design, 2014

2013
Fault mitigation strategies for CUDA GPUs.
Proceedings of the 2013 IEEE International Test Conference, 2013

Increasing the robustness of CUDA Fermi GPU-based systems.
Proceedings of the 2013 IEEE 19th International On-Line Testing Symposium (IOLTS), 2013

SAFE: A self adaptive frame enhancer FPGA-based IP-core for real-time space applications.
Proceedings of the 8th International Design and Test Symposium, 2013

ZipStream: Improving dependability in dynamic partial reconfiguration.
Proceedings of the 8th International Design and Test Symposium, 2013

FEMIP: A high performance FPGA-based features extractor & matcher for space applications.
Proceedings of the 23rd International Conference on Field programmable Logic and Applications, 2013

Dependable Dynamic Partial Reconfiguration with minimal area & time overheads on Xilinx FPGAS.
Proceedings of the 23rd International Conference on Field programmable Logic and Applications, 2013

A software-based self test of CUDA Fermi GPUs.
Proceedings of the 18th IEEE European Test Symposium, 2013

2011
An area-efficient 2-D convolution implementation on FPGA for space applications.
Proceedings of the 6th IEEE International Design and Test Workshop, 2011

Validation & Verification of an EDA automated synthesis tool.
Proceedings of the 6th IEEE International Design and Test Workshop, 2011

A unifying formalism to support automated synthesis of SBSTs for embedded caches.
Proceedings of the 9th East-West Design & Test Symposium, 2011

MarciaTesta: An Automatic Generator of Test Programs for Microprocessors' Data Caches.
Proceedings of the 20th IEEE Asian Test Symposium, 2011


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