Haralampos-G. D. Stratigopoulos

Orcid: 0000-0002-9943-5607

According to our database1, Haralampos-G. D. Stratigopoulos authored at least 111 papers between 2003 and 2023.

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Bibliography

2023
Compact Functional Testing for Neuromorphic Computing Circuits.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., July, 2023

Testability and Dependability of AI Hardware: Survey, Trends, Challenges, and Perspectives.
IEEE Des. Test, April, 2023

Special Issue on Testability and Dependability of Artificial Intelligence Hardware.
IEEE Des. Test, April, 2023

Anti-Piracy Design of RF Transceivers.
IEEE Trans. Circuits Syst. I Regul. Pap., January, 2023

Leaking Wireless ICs via Hardware Trojan-Infected Synchronization.
IEEE Trans. Dependable Secur. Comput., 2023

On-Line Testing of Neuromorphic Hardware.
Proceedings of the IEEE European Test Symposium, 2023

Testing and Reliability of Spiking Neural Networks: A Review of the State-of-the-Art.
Proceedings of the IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2023

2022
RF Transceiver Security Against Piracy Attacks.
IEEE Trans. Circuits Syst. II Express Briefs, 2022

Digital-to-Analog Hardware Trojan Attacks.
IEEE Trans. Circuits Syst. I Regul. Pap., 2022

Digitally Assisted Mixed-Signal Circuit Security.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022

Run-Time Hardware Trojan Detection in Analog and Mixed-Signal ICs.
Proceedings of the 40th IEEE VLSI Test Symposium, 2022

Circuit-to-Circuit Attacks in SoCs via Trojan-Infected IEEE 1687 Test Infrastructure.
Proceedings of the IEEE International Test Conference, 2022

Reliability Analysis of a Spiking Neural Network Hardware Accelerator.
Proceedings of the 2022 Design, Automation & Test in Europe Conference & Exhibition, 2022

SyncLock: RF Transceiver Security Using Synchronization Locking.
Proceedings of the 2022 Design, Automation & Test in Europe Conference & Exhibition, 2022

Anti-Piracy of Analog and Mixed-Signal Circuits in FD-SOI.
Proceedings of the 27th Asia and South Pacific Design Automation Conference, 2022

2021
Locking by Untuning: A Lock-Less Approach for Analog and Mixed-Signal IC Security.
IEEE Trans. Very Large Scale Integr. Syst., 2021

SymBIST: Symmetry-Based Analog and Mixed-Signal Built-In Self-Test for Functional Safety.
IEEE Trans. Circuits Syst. I Regul. Pap., 2021

Analog and Mixed-Signal IC Security via Sizing Camouflaging.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2021

Neuron-PUF: Physical Unclonable Function Based on a Single Spiking Neuron.
Proceedings of the 27th IEEE International Symposium on On-Line Testing and Robust System Design, 2021

BIST-Assisted Analog Fault Diagnosis.
Proceedings of the 26th IEEE European Test Symposium, 2021

Neuron Fault Tolerance in Spiking Neural Networks.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2021

Breaking Analog Biasing Locking Techniques via Re-Synthesis.
Proceedings of the ASPDAC '21: 26th Asia and South Pacific Design Automation Conference, 2021

2020
Spiking Neuron Hardware-Level Fault Modeling.
Proceedings of the 26th IEEE International Symposium on On-Line Testing and Robust System Design, 2020

Hardware Trojan Attacks in Analog/Mixed-Signal ICs via the Test Access Mechanism.
Proceedings of the IEEE European Test Symposium, 2020

Symmetry-based A/M-S BIST (SymBIST): Demonstration on a SAR ADC IP.
Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020

Securing Programmable Analog ICs Against Piracy.
Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020

2019
IP Session on Machine Learning Applications in IC Test-Related Tasks.
Proceedings of the 37th IEEE VLSI Test Symposium, 2019

Mixed-Signal Hardware Security Using MixLock: Demonstration in an Audio Application.
Proceedings of the 16th International Conference on Synthesis, 2019

Self-Testing Analog Spiking Neuron Circuit.
Proceedings of the 16th International Conference on Synthesis, 2019

MixLock: Securing Mixed-Signal Circuits via Logic Locking.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019

2018
Adaptive Test With Test Escape Estimation for Mixed-Signal ICs.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018

Special session on machine learning: How will machine learning transform test?
Proceedings of the 36th IEEE VLSI Test Symposium, 2018

Open Source Hardware and EDA Tools for Analog/Mixed-Signal Design and Prototyping.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

Machine learning applications in IC testing.
Proceedings of the 23rd IEEE European Test Symposium, 2018

2017
Yield Forecasting Across Semiconductor Fabrication Plants and Design Generations.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2017

Recap of the European Test Symposium 2017 (ETS'17).
IEEE Des. Test, 2017

Adaptive test flow for mixed-signal ICs.
Proceedings of the 35th IEEE VLSI Test Symposium, 2017

Foreword.
Proceedings of the 22nd IEEE European Test Symposium, 2017

2016
A Fully-Digital BIST Wrapper Based on Ternary Test Stimuli for the Dynamic Test of a 40 nm CMOS 18-bit Stereo Audio ΣΔ ADC.
IEEE Trans. Circuits Syst. I Regul. Pap., 2016

One-Shot Non-Intrusive Calibration Against Process Variations for Analog/RF Circuits.
IEEE Trans. Circuits Syst. I Regul. Pap., 2016

A 65nm CMOS Ramp Generator Design and its Application Towards a BIST Implementation of the Reduced-Code Static Linearity Test Technique for Pipeline ADCs.
J. Electron. Test., 2016

Guest Editors' Introduction: Top Papers from the 2015 International Test Conference.
IEEE Des. Test, 2016

Practical Simulation Flow for Evaluating Analog/Mixed-Signal Test Techniques.
IEEE Des. Test, 2016

Harnessing fabrication process signature for predicting yield across designs.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016

ETS 2016 foreword.
Proceedings of the 21th IEEE European Test Symposium, 2016

Built-in test of millimeter-Wave circuits based on non-intrusive sensors.
Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016

2015
Exploiting Pipeline ADC Properties for a Reduced-Code Linearity Test Technique.
IEEE Trans. Circuits Syst. I Regul. Pap., 2015

Parametric Built-In Test for 65nm RF LNA Using Non-Intrusive Variation-Aware Sensors.
J. Electron. Test., 2015

Evaluation of low-cost mixed-signal test techniques for circuits with long simulation times.
Proceedings of the 2015 IEEE International Test Conference, 2015

Test and Calibration of RF Circuits Using Built-in Non-intrusive Sensors.
Proceedings of the 2015 IEEE Computer Society Annual Symposium on VLSI, 2015

Yield Forecasting in Fab-to-Fab Production Migration Based on Bayesian Model Fusion.
Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2015

High frequency jitter estimator for SoCs.
Proceedings of the 20th IEEE European Test Symposium, 2015

Fast deployment of alternate analog test using Bayesian model fusion.
Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015

2014
Fast Monte Carlo-Based Estimation of Analog Parametric Test Metrics.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2014

Efficient Monte Carlo-based analog parametric fault modelling.
Proceedings of the 32nd IEEE VLSI Test Symposium, 2014

Statistical Evaluation of Digital Techniques for $\sum\varDelta$ ADC BIST.
Proceedings of the VLSI-SoC: Internet of Things Foundations, 2014

Evaluation of digital ternary stimuli for dynamic test of ΣΔ ADCs.
Proceedings of the 22nd International Conference on Very Large Scale Integration, 2014

Review of temperature sensors as monitors for RF-MMW built-in testing and self-calibration schemes.
Proceedings of the IEEE 57th International Midwest Symposium on Circuits and Systems, 2014

Solutions for the self-adaptation of communicating systems in operation.
Proceedings of the 2014 IEEE 20th International On-Line Testing Symposium, 2014

Low-cost EVM built-in test of RF transceivers.
Proceedings of the 9th International Design and Test Symposium, 2014

One-Shot Calibration of RF Circuits Based on Non-Intrusive Sensors.
Proceedings of the 51st Annual Design Automation Conference 2014, 2014

2013
Reduced-Code Linearity Testing of Pipeline ADCs.
IEEE Des. Test, 2013

Reduced code linearity testing of pipeline adcs in the presence of noise.
Proceedings of the 31st IEEE VLSI Test Symposium, 2013

Defect-oriented non-intrusive RF test using on-chip temperature sensors.
Proceedings of the 31st IEEE VLSI Test Symposium, 2013

Fault modeling and diagnosis for nanometric analog circuits.
Proceedings of the 2013 IEEE International Test Conference, 2013

True non-intrusive sensors for RF built-in test.
Proceedings of the 2013 IEEE International Test Conference, 2013

Multivariate statistical techniques for analog parametric test metrics estimation.
Proceedings of the 8th International Conference on Design & Technology of Integrated Systems in Nanoscale Era, 2013

Multidimensional analog test metrics estimation using extreme value theory and statistical blockade.
Proceedings of the 50th Annual Design Automation Conference 2013, 2013

2012
Diagnosis of Local Spot Defects in Analog Circuits.
IEEE Trans. Instrum. Meas., 2012

Test Metrics Model for Analog Test Development.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2012

Guest Editors' Introduction: Digitally Enhanced Wireless Transceivers.
IEEE Des. Test Comput., 2012

Adaptive Alternate Analog Test.
IEEE Des. Test Comput., 2012

Experiences with non-intrusive sensors for RF built-in test.
Proceedings of the 2012 IEEE International Test Conference, 2012

Enhanced reduced code linearity test technique for multi-bit/stage pipeline ADCs.
Proceedings of the 17th IEEE European Test Symposium, 2012

Advances in variation-aware modeling, verification, and testing of analog ICs.
Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012

Testing RF circuits with true non-intrusive built-in sensors.
Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012

2011
Estimation of Analog Parametric Test Metrics Using Copulas.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2011

Guest Editorial.
J. Electron. Test., 2011

RF Front-End Test Using Built-in Sensors.
IEEE Des. Test Comput., 2011

On proving the efficiency of alternative RF tests.
Proceedings of the 2011 IEEE/ACM International Conference on Computer-Aided Design, 2011

Implicit test of high-speed analog circuits using non-intrusive sensors.
Proceedings of the 20th European Conference on Circuit Theory and Design, 2011

On Replacing an RF Test with an Alternative Measurement: Theory and a Case Study.
Proceedings of the 20th IEEE Asian Test Symposium, 2011

2010
RF Specification Test Compaction Using Learning Machines.
IEEE Trans. Very Large Scale Integr. Syst., 2010

Special session 12A: Panel adaptive analog test: Feasibility and opportunities ahead.
Proceedings of the 28th IEEE VLSI Test Symposium, 2010

Special session 8A: TTTC 2010 E. J. McCluskey Best Doctoral Thesis Award.
Proceedings of the 28th IEEE VLSI Test Symposium, 2010

Special session 4C: Thesis research poster session.
Proceedings of the 28th IEEE VLSI Test Symposium, 2010

Density estimation for analog/RF test problem solving.
Proceedings of the 28th IEEE VLSI Test Symposium, 2010

Analog neural network design for RF built-in self-test.
Proceedings of the 2011 IEEE International Test Conference, 2010

An analog VLSI multilayer perceptron and its application towards built-in self-test in analog circuits.
Proceedings of the 16th IEEE International On-Line Testing Symposium (IOLTS 2010), 2010

Analog test metrics estimates with PPM accuracy.
Proceedings of the 2010 International Conference on Computer-Aided Design, 2010

Sensors for built-in alternate RF test.
Proceedings of the 15th European Test Symposium, 2010

Fault diagnosis of analog circuits based on machine learning.
Proceedings of the Design, Automation and Test in Europe, 2010

Bayesian Fault Diagnosis of RF Circuits Using Nonparametric Density Estimation.
Proceedings of the 19th IEEE Asian Test Symposium, 2010

2009
Evaluation of Analog/RF Test Measurements at the Design Stage.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2009

Special Session 7C: TTTC 2009 Best Doctoral Thesis Contest.
Proceedings of the 27th IEEE VLSI Test Symposium, 2009

Hierarchical parametric test metrics estimation: A ΣΔ converter BIST case study.
Proceedings of the 27th International Conference on Computer Design, 2009

Defect Filter for Alternate RF Test.
Proceedings of the 14th IEEE European Test Symposium, 2009

Enrichment of limited training sets in machine-learning-based analog/RF test.
Proceedings of the Design, Automation and Test in Europe, 2009

2008
Error Moderation in Low-Cost Machine-Learning-Based Analog/RF Testing.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2008

A Statistical Approach to Characterizing and Testing Functionalized Nanowires.
Proceedings of the 26th IEEE VLSI Test Symposium (VTS 2008), April 27, 2008

A General Method to Evaluate RF BIST Techniques Based on Non-parametric Density Estimation.
Proceedings of the Design, Automation and Test in Europe, 2008

2007
Non-RF to RF Test Correlation Using Learning Machines: A Case Study.
Proceedings of the 25th IEEE VLSI Test Symposium (VTS 2007), 2007

2006
Concurrent detection of erroneous responses in linear analog circuits.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006

An adaptive checker for the fully differential analog code.
IEEE J. Solid State Circuits, 2006

Bridging the Accuracy of Functional and Machine-Learning-Based Mixed-Signal Testing.
Proceedings of the 24th IEEE VLSI Test Symposium (VTS 2006), 30 April, 2006

2005
Nonlinear decision boundaries for testing analog circuits.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2005

Constructive Derivation of Analog Specification Test Criteria.
Proceedings of the 23rd IEEE VLSI Test Symposium (VTS 2005), 2005

Generating decision regions in analog measurement spaces.
Proceedings of the 15th ACM Great Lakes Symposium on VLSI 2005, 2005

2004
An Analog Checker with Input-Relative Tolerance for Duplicate Signals.
J. Electron. Test., 2004

2003
An Analog Checker with Dynamically Adjustable Error Threshold for Fully Differential Circuits.
Proceedings of the 21st IEEE VLSI Test Symposium (VTS 2003), 27 April, 2003

Concurrent Error Detection in Linear Analog Circuits Using State Estimation.
Proceedings of the Proceedings 2003 International Test Conference (ITC 2003), Breaking Test Interface Bottlenecks, 28 September, 2003


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