Jwalant Mishra

According to our database, Jwalant Mishra authored at least 5 papers between 2022 and 2025.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2025

Robust Verification Methodology for Scan Chain in Memories.

Rajat Kohli, Umang Deep, Vaishnavi Holla, Jwalant Kumar Mishra

Proceedings of the 38th International Conference on VLSI Design and 2024 23rd International Conference on Embedded Systems, 2025

2024

Multi-Bit Compute-In Memory Architecture Using a C-2C Ladder Network.

Dinesh Kushwaha, Jaya Kumar Abotula, Rajat Kohli, Jwalant Mishra, Sudeb Dasgupta, Anand Bulusu

IEEE Trans. Circuits Syst. II Express Briefs, June, 2024

An Energy-Efficient High Signal Margin Analog Compute-In-Memory Architecture.

Dinesh Kushwaha, Rajat Kohli, Jwalant Mishra, Jainendra Singh, Rajiv V. Joshi, Sudeb Dasgupta, Anand Bulusu

Proceedings of the 15th IEEE Latin America Symposium on Circuits and Systems, 2024

2023

A Fully Differential 4-Bit Analog Compute-In-Memory Architecture for Inference Application.

Dinesh Kushwaha, Rajat Kohli, Jwalant Mishra, Rajiv V. Joshi, Sudeb Dasgupta, Anand Bulusu

Proceedings of the 5th IEEE International Conference on Artificial Intelligence Circuits and Systems, 2023

2022

A 65nm Compute-In-Memory 7T SRAM Macro Supporting 4-bit Multiply and Accumulate Operation by Employing Charge Sharing.

Dinesh Kushwaha, Aditya Sharma, Neha Gupta, Ritik Raj, Ashish Joshi, Jwalant Mishra, Rajat Kohli, Sandeep Miryala, Rajiv V. Joshi, Sudeb Dasgupta, Anand Bulusu

Proceedings of the IEEE International Symposium on Circuits and Systems, 2022