Jyi-Tsong Lin

According to our database, Jyi-Tsong Lin authored at least 11 papers between 2006 and 2023.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2023

An iTFET with Control Gate for Low Power Applications in RF and Digital Circuits.

Ho-Hin Tse, Zheng-Hong Zhong, Jyi-Tsong Lin

Proceedings of the 15th IEEE International Conference on ASIC, 2023

A Simple New Line-Tunneling iTFET with Overlapping Between Gate and Source Contact.

Jyi-Tsong Lin, Kuan-Pin Lin

Proceedings of the 15th IEEE International Conference on ASIC, 2023

Steeper Subthreshold Swing Attained in Ge-Source Inductive Tunneling FET via Epitaxial Tunnel Layer for Suppressed Point Tunneling.

Yen-Chen Chang, Wei-Heng Tai, Jyi-Tsong Lin

Proceedings of the 15th IEEE International Conference on ASIC, 2023

2020

Performances Improvement of Tunneling Field-Effect Transistors' with the Advanced Double-Gate PN Construction.

Yu-Jen Chen, Jyi-Tsong Lin

Proceedings of the IEEE International Conference on Consumer Electronics - Taiwan, 2020

2018

Emerging FETs for Low Power and High Speed Embedded Dynamic Random Access Memory.

Md. Hasan Raza Ansari, Nupur Navlakha, Jyi-Tsong Lin, Abhinav Kranti

Proceedings of the 31st International Conference on VLSI Design and 17th International Conference on Embedded Systems, 2018

2017

Threshold-voltage variability analysis and modeling for junctionless double-gate transistors.

Chun-Yu Chen, Jyi-Tsong Lin, Meng-Hsueh Chiang

Microelectron. Reliab., 2017

2015

Using GIDL mechanism for low-power consumption and data retention time improvement in a double-gate nanowire TFT 1T-DRAM with Fin-Gate and Pillar-Body structure.

Wei-Han Lee, Jyi-Tsong Lin, Yu-Chun Wang, Po-Hsieh Lin, Chien-Chia Lai, Yong-Huang Lin, Tin-Chun Chang

Proceedings of the 2015 IEEE 11th International Conference on ASIC, 2015

2011

A unipolar-CMOS with recessed source/drain load.

Jyi-Tsong Lin, Hsuan-Hsu Chen, Kuan-Yu Lu, Chih-Hung Sun, Tung-Yen Lai, Fu-Liang Yang

Proceedings of the 2011 IEEE 9th International Conference on ASIC, 2011

2008

Analysis of Block Oxide Height Variations for a 40nm Gate Length bFDSOI-FET.

Jyi-Tsong Lin, Yi-Chuen Eng

J. Comput., 2008

2007

Analysis of Si-body thickness variation for a new 40 nm gate length bFDSOI.

Jyi-Tsong Lin, Yi-Chuen Eng, Tai-Yi Lee, Kao-Cheng Lin

Proceedings of the 20th International Conference on VLSI Design (VLSI Design 2007), 2007

2006

A New 1T DRAM Cell With Enhanced Floating Body Ef.

Jyi-Tsong Lin, Mike Chang

Proceedings of the 14th IEEE International Workshop on Memory Technology, 2006