Meng-Hsueh Chiang

According to our database, Meng-Hsueh Chiang authored at least 15 papers between 2010 and 2024.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2024

Fabrication of Hybrid Fin/Planar LDMOS with Modulation Gate.

Zih-Fei Chen, Ya-Chi Huang, Yu-Shen Lai, Yi-Ting Wu, Cheng-Ming Huang, Meng-Hsueh Chiang

Proceedings of the Device Research Conference, 2024

2023

How Fault-Tolerant Quantum Computing Benefits from Cryo-CMOS Technology.

H.-L. Chiang, Richard A. Hadi, J.-F. Wang, H.-C. Han, J.-J. Wu, H.-H. Hsieh, J.-J. Horng, W.-S. Chou, B.-S. Lien, C.-H. Chang, Y.-C. Chen, Yeong-Her Wang, T.-C. Chen, J.-C. Liu, Y.-C. Liu, Meng-Hsueh Chiang, K.-H. Kao, B. Pulicherla, J. Cai, C.-S. Chang, K.-W. Su, K.-L. Cheng, T.-J. Yeh, Y.-C. Peng, C. Enz, Mau-Chung Frank Chang, M.-F. Chang, H.-S. Philip Wong, Iuliana P. Radu

Proceedings of the 2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), 2023

MOSFET Characterization with Reduced Supply Voltage at Low Temperatures for Power Efficiency Maximization.

W.-C. Lin, H.-P. Huang, Kuo-Hsing Kao, Meng-Hsueh Chiang, Darsen D. Lu, Wei-Chou Hsu, Yeong-Her Wang, William Cheng-Yu Ma, Hann-Huei Tsai, Y.-J. Lee, H.-L. Chiang, J.-F. Wang, Iuliana P. Radu

Proceedings of the 53rd IEEE European Solid-State Device Research Conference, 2023

Performance Comparison of SRAM Designs Implemented with Silicon-On-Insulator Nanosheet Transistors and Bulk FinFETs.

Po-Chih Chen, Yi-Ting Wu, Meng-Hsueh Chiang

Proceedings of the 53rd IEEE European Solid-State Device Research Conference, 2023

2021

Back-Bias Modulated UTBB SOI for System-on-Chip I/O Cells.

Ming-Yu Chang, Po-Yu Chao, Meng-Hsueh Chiang

Proceedings of the 22nd International Symposium on Quality Electronic Design, 2021

2020

Compact Device Models for FinFET and Beyond.

Darsen D. Lu, Mohan V. Dunga, Ali M. Niknejad, Chenming Hu, Fu-Xiang Liang, Wei-Chen Hung, Jia-Wei Lee, Chun-Hsiang Hsu, Meng-Hsueh Chiang

CoRR, 2020

2019

Speed Optimization of Vertically Stacked Gate-All-Around MOSFETs with Inner Spacers for Low Power and Ultra-Low Power Applications.

Ya-Chi Huang, Meng-Hsueh Chiang, Shui-Jinn Wang

Proceedings of the 20th International Symposium on Quality Electronic Design, 2019

2018

Body-biasing assisted vmin optimization for 5nm-node multi-Vt FD-SOI 6T-SRAM.

Jheng-Yi Chen, Ming-Yu Chang, Shi-Hao Chen, Jia-Wei Lee, Meng-Hsueh Chiang

Proceedings of the 19th International Symposium on Quality Electronic Design, 2018

An area efficient low-voltage 6-T SRAM cell using stacked silicon nanowires.

Ya-Chi Huang, Meng-Hsueh Chiang, Shui-Jinn Wang, Sumeet Kumar Gupta

Proceedings of the 2018 International Conference on IC Design & Technology, 2018

2017

Threshold-voltage variability analysis and modeling for junctionless double-gate transistors.

Chun-Yu Chen, Jyi-Tsong Lin, Meng-Hsueh Chiang

Microelectron. Reliab., 2017

2016

Performance evaluation of stacked gate-all-around MOSFETs at 7 and 10 nm technology nodes.

Meng-Yen Wu, Meng-Hsueh Chiang

Proceedings of the 17th International Symposium on Quality Electronic Design, 2016

2015

6-T SRAM performance assessment with stacked silicon nanowire MOSFETs.

Ya-Chi Huang, Meng-Hsueh Chiang, Wei-Chou Hsu, Shiou-Ying Cheng

Proceedings of the Sixteenth International Symposium on Quality Electronic Design, 2015

2012

Assessment of structure variation in silicon nanowire FETs and impact on SRAM.

Yi-Bo Liao, Meng-Hsueh Chiang, Keunwoo Kim, Wei-Chou Hsu

Microelectron. J., 2012

Design issues and insights of multi-fin bulk silicon FinFETs.

Hsun Li, Meng-Hsueh Chiang

Proceedings of the Thirteenth International Symposium on Quality Electronic Design, 2012

2010

Low power design of phase-change memory based on a comprehensive model.

Meng-Hsueh Chiang, Yi-Bo Liao, Jun-Tin Lin, Wei-Chou Hsu, Chu Yu, Pei-Chia Chiang, Y.-Y. Hsu, W.-H. Liu, Shyh-Shyuan Sheu, Keng-Li Su, Ming-Jer Kao, Ming-Jinn Tsai

IET Comput. Digit. Tech., 2010