Kao-Cheng Lin

According to our database, Kao-Cheng Lin authored at least 5 papers between 2007 and 2019.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2019

A 7nm 2.1GHz Dual-Port SRAM with WL-RC Optimization and Dummy-Read-Recovery Circuitry to Mitigate Read- Disturb-Write Issue.

Hidehiro Fujiwara, Chih-Yu Lin, Hsien-Yu Pan, Cheng-Han Lin, Po-Yi Huang, Kao-Cheng Lin, Jhon-Jhy Liaw, Yen-Huei Chen, Hung-Jen Liao, Jonathan Chang

Proceedings of the IEEE International Solid- State Circuits Conference, 2019

2017

12.1 A 7nm 256Mb SRAM in high-k metal-gate FinFET technology with write-assist circuitry for low-VMIN applications.

Jonathan Chang, Yen-Huei Chen, Wei-Min Chan, Sahil Preet Singh, Hank Cheng, Hidehiro Fujiwara, Jih-Yu Lin, Kao-Cheng Lin, John Hung, Robin Lee, Hung-Jen Liao, Jhon-Jhy Liaw, Quincy Li, Chih-Yung Lin, Mu-Chi Chiang, Shien-Yang Wu

Proceedings of the 2017 IEEE International Solid-State Circuits Conference, 2017

2016

A 16nm dual-port SRAM with partial suppressed word-line, dummy read recovery and negative bit-line circuitries for low VMIN applications.

Yen-Huei Chen, Kao-Cheng Lin, Ching-Wei Wu, Wei-Min Chan, Jhon-Jhy Liaw, Hung-Jen Liao, Jonathan Chang

Proceedings of the 2016 IEEE Symposium on VLSI Circuits, 2016

2015

17.2 A 64kb 16nm asynchronous disturb current free 2-port SRAM with PMOS pass-gates for FinFET technologies.

Hidehiro Fujiwara, Li-Wen Wang, Yen-Huei Chen, Kao-Cheng Lin, Dar Sun, Shin-Rung Wu, Jhon-Jhy Liaw, Chih-Yung Lin, Mu-Chi Chiang, Hung-Jen Liao, Shien-Yang Wu, Jonathan Chang

Proceedings of the 2015 IEEE International Solid-State Circuits Conference, 2015

2007

Analysis of Si-body thickness variation for a new 40 nm gate length bFDSOI.

Jyi-Tsong Lin, Yi-Chuen Eng, Tai-Yi Lee, Kao-Cheng Lin

Proceedings of the 20th International Conference on VLSI Design (VLSI Design 2007), 2007