Kai-Wen Yao

According to our database1, Kai-Wen Yao authored at least 15 papers between 2007 and 2017.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

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PhD thesis 
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Links

On csauthors.net:

Bibliography

2017
A body sensor node SoC for ECG/EMG applications with compressed sensing and wireless powering.
Proceedings of the 2017 International Symposium on VLSI Design, Automation and Test, 2017

2015
A bandwidth-tunable bioamplifier with voltage-controlled symmetric pseudo-resistors.
Microelectron. J., 2015

2013
A CMOS multichannel electrical stimulation prototype system.
Int. J. Circuit Theory Appl., 2013

A sigma-delta modulator for bio-applications.
Proceedings of the IEEE International Symposium on Consumer Electronics, 2013

2012
On investigation into A CMOS-process-based high-voltage driver applied to implantable microsystem.
Proceedings of Technical Program of 2012 VLSI Design, Automation and Test, 2012

Adiabatic technique for biomedical applications.
Proceedings of the International Symposium on Intelligent Signal Processing and Communications Systems, 2012

An impedance measurement analog front end for wirelessly bioimplantable applications.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2012

2011
Design of a neural recording amplifier with tunable pseudo resistors.
Proceedings of the IEEE 24th International SoC Conference, SOCC 2011, Taipei, Taiwan, 2011

CMOS comparator for medical imaging.
Proceedings of the 4th International Conference on Biomedical Engineering and Informatics, 2011

2008
A Truly Low-Cost High-Efficiency ASK Demodulator Based on Self-Sampling Scheme for Bioimplantable Applications.
IEEE Trans. Circuits Syst. I Regul. Pap., 2008

Analysis and Design of an Efficient Irreversible Energy Recovery Logic in 0.18-mum CMOS.
IEEE Trans. Circuits Syst. I Regul. Pap., 2008

A compact and low-power SRAM with improved read static noise margin.
Proceedings of the 15th IEEE International Conference on Electronics, Circuits and Systems, 2008

An efficiency-enhanced CMOS voltage regulator module for bio-electronic implants.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2008

A low-power area-efficient SRAM with enhanced read stability in 0.18-μm CMOS.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2008

2007
Analysis and design of an efficient complementary energy path adiabatic logic for low-power system applications.
Proceedings of the 2007 IEEE International SOC Conference, 2007


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