Yi-Min Jiang

According to our database, Yi-Min Jiang authored at least 21 papers between 1992 and 2022.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2022

Congestion and Timing Aware Macro Placement Using Machine Learning Predictions from Different Data Sources: Cross-design Model Applicability and the Discerning Ensemble.

Xiang Gao, Yi-Min Jiang, Lixin Shao, Pedja Raspopovic, Menno E. Verbeek, Manish Sharma, Vineet Rashingkar, Amit Jalota

Proceedings of the ISPD 2022: International Symposium on Physical Design, Virtual Event, Canada, March 27, 2022

2014

A method of batching conflict routings in shuffle-exchange networks.

Yi-Hao Zhang, Yue-Hong Shen, Min Dong, Yi-Min Jiang

Theor. Comput. Sci., 2014

2008

Simultaneous Sleep Transistor Insertion and Power Network Synthesis for Industrial Power Gating Designs.

Kaijian Shi, Zhian Lin, Yi-Min Jiang, Lin Yuan

J. Comput., 2008

2007

A Power Network Synthesis Method for Industrial Power Gating Designs.

Kaijian Shi, Zhian Lin, Yi-Min Jiang

Proceedings of the 8th International Symposium on Quality of Electronic Design (ISQED 2007), 2007

2003

Modeling, testing, and analysis for delay defects and noise effects in deep submicron devices.

Jing-Jia Liou, Angela Krstic, Yi-Min Jiang, Kwang-Ting Cheng

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2003

2001

Vector generation for power supply noise estimation and verification of deep submicron designs.

Yi-Min Jiang, Kwang-Ting Cheng

IEEE Trans. Very Large Scale Integr. Syst., 2001

Pattern generation for delay testing and dynamic timing analysisconsidering power-supply noise effects.

Angela Krstic, Yi-Min Jiang, Kwang-Ting Cheng

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2001

Delay testing considering crosstalk-induced effects.

Angela Krstic, Jing-Jia Liou, Yi-Min Jiang, Kwang-Ting Cheng

Proceedings of the Proceedings IEEE International Test Conference 2001, Baltimore, MD, USA, 30 October, 2001

HRM - A Hierarchical Simulator for Full-Chip Power Network Reliability Analysis.

Yi-Min Jiang, Han Young Koh, Kwang-Ting Cheng

Proceedings of the 2nd International Symposium on Quality of Electronic Design (ISQED 2001), 2001

2000

Estimation for maximum instantaneous current through supply lines for CMOS circuits.

Yi-Min Jiang, Angela Krstic, Kwang-Ting Cheng

IEEE Trans. Very Large Scale Integr. Syst., 2000

Dynamic Timing Analysis Considering Power Supply Noise Effects.

Yi-Min Jiang, Angela Krstic, Kwang-Ting Cheng

Proceedings of the 1st International Symposium on Quality of Electronic Design (ISQED 2000), 2000

Path Selection and Pattern Generation for Dynamic Timing Analysis Considering Power Supply Noise Effects.

Jing-Jia Liou, Angela Krstic, Yi-Min Jiang, Kwang-Ting Cheng

Proceedings of the 2000 IEEE/ACM International Conference on Computer-Aided Design, 2000

1999

Delay testing considering power supply noise effects.

Yi-Min Jiang, Angela Krstic, Kwang-Ting Cheng

Proceedings of the Proceedings IEEE International Test Conference 1999, 1999

VIP - an input pattern generator for indentifying critical voltage drop for deep sub-micron designs.

Yi-Min Jiang, Tak K. Young, Kwang-Ting Cheng

Proceedings of the 1999 International Symposium on Low Power Electronics and Design, 1999

Analysis of Performance Impact Caused by Power Supply Noise in Deep Submicron Devices.

Yi-Min Jiang, Kwang-Ting Cheng

Proceedings of the 36th Conference on Design Automation, 1999

1998

Estimation of maximum power supply noise for deep sub-micron designs.

Yi-Min Jiang, Kwang-Ting Cheng, An-Chang Deng

Proceedings of the 1998 International Symposium on Low Power Electronics and Design, 1998

Exact and Approximate Estimation for Maximum Instantaneous Current of CMOS Circuits.

Yi-Min Jiang, Kwang-Ting Cheng

Proceedings of the 1998 Design, 1998

A Hybrid Power Model for RTL Power Estimation.

Yi-Min Jiang, Shi-Yu Huang, Kwang-Ting Cheng, Deborah C. Wang, ChingYen Ho

Proceedings of the ASP-DAC '98, 1998

1997

Post-Layout Logic Restructuring for Performance Optimization.

Yi-Min Jiang, Angela Krstic, Kwang-Ting Cheng, Malgorzata Marek-Sadowska

Proceedings of the 34st Conference on Design Automation, 1997

1994

Performance-driven interconnection optimization for microarchitecture synthesis.

Yi-Min Jiang, Tsing-Fa Lee, TingTing Hwang, Youn-Long Lin

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1994

1992

Performance-driven interconnection optimization for microarchitecture synthesis.

Yi-Min Jiang, Tsing-Fa Lee, TingTing Hwang, Yaun-Long Lin

Proceedings of the conference on European design automation, 1992