Yi-Min Jiang

According to our database1, Yi-Min Jiang authored at least 20 papers between 1992 and 2014.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Other 

Links

On csauthors.net:

Bibliography

2014
A method of batching conflict routings in shuffle-exchange networks.
Theor. Comput. Sci., 2014

2008
Simultaneous Sleep Transistor Insertion and Power Network Synthesis for Industrial Power Gating Designs.
J. Comput., 2008

2007
A Power Network Synthesis Method for Industrial Power Gating Designs.
Proceedings of the 8th International Symposium on Quality of Electronic Design (ISQED 2007), 2007

2003
Modeling, testing, and analysis for delay defects and noise effects in deep submicron devices.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2003

2001
Vector generation for power supply noise estimation and verification of deep submicron designs.
IEEE Trans. Very Large Scale Integr. Syst., 2001

Pattern generation for delay testing and dynamic timing analysisconsidering power-supply noise effects.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2001

Delay testing considering crosstalk-induced effects.
Proceedings of the Proceedings IEEE International Test Conference 2001, Baltimore, MD, USA, 30 October, 2001

HRM - A Hierarchical Simulator for Full-Chip Power Network Reliability Analysis.
Proceedings of the 2nd International Symposium on Quality of Electronic Design (ISQED 2001), 2001

2000
Estimation for maximum instantaneous current through supply lines for CMOS circuits.
IEEE Trans. Very Large Scale Integr. Syst., 2000

Dynamic Timing Analysis Considering Power Supply Noise Effects.
Proceedings of the 1st International Symposium on Quality of Electronic Design (ISQED 2000), 2000

Path Selection and Pattern Generation for Dynamic Timing Analysis Considering Power Supply Noise Effects.
Proceedings of the 2000 IEEE/ACM International Conference on Computer-Aided Design, 2000

1999
Delay testing considering power supply noise effects.
Proceedings of the Proceedings IEEE International Test Conference 1999, 1999

VIP - an input pattern generator for indentifying critical voltage drop for deep sub-micron designs.
Proceedings of the 1999 International Symposium on Low Power Electronics and Design, 1999

Analysis of Performance Impact Caused by Power Supply Noise in Deep Submicron Devices.
Proceedings of the 36th Conference on Design Automation, 1999

1998
Estimation of maximum power supply noise for deep sub-micron designs.
Proceedings of the 1998 International Symposium on Low Power Electronics and Design, 1998

Exact and Approximate Estimation for Maximum Instantaneous Current of CMOS Circuits.
Proceedings of the 1998 Design, 1998

A Hybrid Power Model for RTL Power Estimation.
Proceedings of the ASP-DAC '98, 1998

1997
Post-Layout Logic Restructuring for Performance Optimization.
Proceedings of the 34st Conference on Design Automation, 1997

1994
Performance-driven interconnection optimization for microarchitecture synthesis.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1994

1992
Performance-driven interconnection optimization for microarchitecture synthesis.
Proceedings of the conference on European design automation, 1992


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