Robert C. Aitken

According to our database1, Robert C. Aitken authored at least 123 papers between 1988 and 2019.

Collaborative distances:

Awards

IEEE Fellow

IEEE Fellow 2013, "For contributions to testing and diagnosis of integrated circuits".

Timeline

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In proceedings 
Article 
PhD thesis 
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Links

On csauthors.net:

Bibliography

2019
Special Section on Emerging Trends and Design Paradigms for Memory Systems and Storage.
IEEE Trans. Emerg. Top. Comput., 2019

56th Design Automation Conference Report.
IEEE Des. Test, 2019

Challenges and Opportunities for Efficient Serverless Computing at the Edge.
Proceedings of the 38th Symposium on Reliable Distributed Systems, 2019

Analysis and Demand Forecasting of Residential Energy Consumption at Multiple Time Scales.
Proceedings of the IFIP/IEEE International Symposium on Integrated Network Management, 2019

Automating Energy Demand Modeling and Forecasting Using Smart Meter Data.
Proceedings of the 2019 IEEE International Congress on Internet of Things, 2019

2017
The road to a trillion: Making the IoT work.
Proceedings of the 2017 International Symposium on VLSI Design, Automation and Test, 2017

Foreword.
Proceedings of the 22nd IEEE European Test Symposium, 2017

2016
Predicting future complementary metal-oxide-semiconductor technology - challenges and approaches.
IET Comput. Digit. Tech., 2016

Test implications and challenges in near threshold computing special session.
Proceedings of the 34th IEEE VLSI Test Symposium, 2016

A 400mV active VMIN, 200mV retention VMIN, 2.8 GHz 64Kb SRAM with a 0.09 um<sup>2</sup> 6T bitcell in a 16nm FinFET CMOS process.
Proceedings of the 2016 IEEE Symposium on VLSI Circuits, 2016

Coordinating Communication, Technology and Design in the IOT Era.
Proceedings of the 2016 International Symposium on Low Power Electronics and Design, 2016

Resiliency in dynamically power managed designs.
Proceedings of the 35th International Conference on Computer-Aided Design, 2016

2015
No Fault Found: The root cause.
Proceedings of the 33rd IEEE VLSI Test Symposium, 2015

Resiliency challenges in sub-10nm technologies.
Proceedings of the 33rd IEEE VLSI Test Symposium, 2015

Panel: Is design-for-security the new DFT?
Proceedings of the 33rd IEEE VLSI Test Symposium, 2015

Circuit design perspectives for Ge FinFET at 10nm and beyond.
Proceedings of the Sixteenth International Symposium on Quality Electronic Design, 2015

Session 12 - Tutorial - beyond CMOS: Large area electronics-concepts and prospects.
Proceedings of the 2015 IEEE Custom Integrated Circuits Conference, 2015

2014
SlackProbe: A Flexible and Efficient In Situ Timing Slack Monitoring Methodology.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2014

Time-Borrowing Circuit Designs and Hardware Prototyping for Timing Error Resilience.
IEEE Trans. Computers, 2014

BTI-Gater: An Aging-Resilient Clock Gating Methodology.
IEEE J. Emerg. Sel. Topics Circuits Syst., 2014

Physical design and FinFETs.
Proceedings of the International Symposium on Physical Design, 2014

A digital dynamic write margin sensor for low power read/write operations in 28nm SRAM.
Proceedings of the International Symposium on Low Power Electronics and Design, 2014

Modeling SRAM dynamic VMIN.
Proceedings of the 2014 IEEE International Conference on IC Design & Technology, 2014

DFM is dead - Long live DFM.
Proceedings of the 32nd IEEE International Conference on Computer Design, 2014

Mobile hardware security.
Proceedings of the 2014 IEEE Hot Chips 26 Symposium (HCS), 2014

Panel: Emerging vs. established technologies, a two sphinxes' riddle at the crossroads?
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014

2013
Hot topic session 4A: Reliability analysis of complex digital systems.
Proceedings of the 31st IEEE VLSI Test Symposium, 2013

Welcome message.
Proceedings of the 2013 IEEE International Test Conference, 2013

SlackProbe: a low overhead in situ on-line timing slack monitoring methodology.
Proceedings of the Design, Automation and Test in Europe, 2013

Leveraging sensitivity analysis for fast, accurate estimation of SRAM dynamic write V<sub>MIN</sub>.
Proceedings of the Design, Automation and Test in Europe, 2013

Reliability analysis reloaded: how will we survive?
Proceedings of the Design, Automation and Test in Europe, 2013

The past present and future of design-technology co-optimization.
Proceedings of the IEEE 2013 Custom Integrated Circuits Conference, 2013

2012
Yield Learning Perspectives.
IEEE Des. Test Comput., 2012

Panel: going green across communications and storage systems: control of power in non-mobile devices.
Proceedings of the International Symposium on Low Power Electronics and Design, 2012

An adaptive write word-line pulse width and voltage modulation architecture for bit-interleaved 8T SRAMs.
Proceedings of the International Symposium on Low Power Electronics and Design, 2012

VLSI Test technology: Why is the field not sexy enough?
Proceedings of the 17th IEEE European Test Symposium, 2012

2011
Variation-aware static and dynamic writability analysis for voltage-scaled bit-interleaved 8-T SRAMs.
Proceedings of the 2011 International Symposium on Low Power Electronics and Design, 2011

Dynamic write limited minimum operating voltage for nanoscale SRAMs.
Proceedings of the Design, Automation and Test in Europe, 2011

Analytical model for SRAM dynamic write-ability degradation due to gate oxide breakdown.
Proceedings of the Design, Automation and Test in Europe, 2011

Correlating models and silicon for improved parametric yield.
Proceedings of the Design, Automation and Test in Europe, 2011

On the impact of gate oxide degradation on SRAM dynamic and static write-ability.
Proceedings of the 16th Asia South Pacific Design Automation Conference, 2011

High-Performance Multiprocessor System on Chip: Trends in Chip Architecture for the Mass Market.
Proceedings of the Multiprocessor System-on-Chip - Hardware Design and Tool Integration., 2011

2010
Time to retire our benchmarks.
IEEE Des. Test Comput., 2010

Modeling the impact of process variation on resistive bridge defects.
Proceedings of the 2011 IEEE International Test Conference, 2010

Asymmetric 6T SRAM with two-phase write and split bitline differential sensing for low voltage operation.
Proceedings of the 11th International Symposium on Quality of Electronic Design (ISQED 2010), 2010

A black box method for stability analysis of arbitrary SRAM cell structures.
Proceedings of the Design, Automation and Test in Europe, 2010

TIMBER: Time borrowing and error relaying for online timing error resilience.
Proceedings of the Design, Automation and Test in Europe, 2010

Analytical model for TDDB-based performance degradation in combinational logic.
Proceedings of the Design, Automation and Test in Europe, 2010

On the efficacy of write-assist techniques in low voltage nanoscale SRAMs.
Proceedings of the Design, Automation and Test in Europe, 2010

Who solves the variability problem?
Proceedings of the 47th Design Automation Conference, 2010

Post-silicon is too late avoiding the $50 million paperweight starts with validated designs.
Proceedings of the 47th Design Automation Conference, 2010

2009
DFX and Productivity.
Proceedings of the VLSI Design 2009: Improving Productivity through Higher Abstraction, 2009

The challenges of correlating silicon and models in high variability CMOS processes.
Proceedings of the 2009 International Symposium on Physical Design, 2009

Impact of voltage scaling on nanoscale SRAM reliability.
Proceedings of the Design, Automation and Test in Europe, 2009

Addressing design margins through error-tolerant circuits.
Proceedings of the 46th Design Automation Conference, 2009

2008
Guest Editors' Introduction: Addressing the Challenges of Debug and Diagnosis.
IEEE Des. Test Comput., 2008

Special Session 4: Reliability and Circuit Simulation.
Proceedings of the 14th IEEE International On-Line Testing Symposium (IOLTS 2008), 2008

More Moore: foolish, feasible, or fundamentally different?
Proceedings of the 2008 International Conference on Computer-Aided Design, 2008

Impact of Technology and Voltage Scaling on the Soft Error Susceptibility in Nanoscale CMOS.
Proceedings of the 23rd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2008), 2008

Panel Session - Caution Ahead: The Road to Design and Manufacturing at 32 and 22 nm.
Proceedings of the Design, Automation and Test in Europe, 2008

DFM in practice: hit or hype?
Proceedings of the 45th Design Automation Conference, 2008

2007
Guest Editorial: Special Section on "Autonomous Silicon Validation and Testing of Microprocessors and Microprocessor-Based Systems".
IEEE Trans. Very Large Scale Integr. Syst., 2007

Defect or Variation? Characterizing Standard Cell Behavior at 90nm and below.
Proceedings of the 8th International Symposium on Quality of Electronic Design (ISQED 2007), 2007

DFM/DFY: should you trust the surgeon or the family doctor?
Proceedings of the 2007 Design, Automation and Test in Europe Conference and Exposition, 2007

Worst-case design and margin for embedded SRAM.
Proceedings of the 2007 Design, Automation and Test in Europe Conference and Exposition, 2007

Low Power Methodology Manual - for System-on-Chip Design.
Springer, ISBN: 978-0-387-71818-7, 2007

2006
The Design and Validation of IP for DFM/DFY Assurance.
Proceedings of the 2006 IEEE International Test Conference, 2006

DFM Metrics for Standard Cells.
Proceedings of the 7th International Symposium on Quality of Electronic Design (ISQED 2006), 2006

Reliability Issues for Embedded SRAM at 90nm and Below.
Proceedings of the 12th IEEE International On-Line Testing Symposium (IOLTS 2006), 2006

Low-power design tools: are EDA vendors taking this matter seriously?
Proceedings of the Conference on Design, Automation and Test in Europe, 2006

2005
ITC is Cool.
IEEE Des. Test Comput., 2005

Modeling Soft-Error Susceptibility for IP Blocks.
Proceedings of the 11th IEEE International On-Line Testing Symposium (IOLTS 2005), 2005

ESD implementation strategies.
Proceedings of the IEEE 2005 Custom Integrated Circuits Conference, 2005

Noise and reliability containment approaches.
Proceedings of the IEEE 2005 Custom Integrated Circuits Conference, 2005

2004
ITC 2003 panels: Part 1.
IEEE Des. Test Comput., 2004

ITC 2003 Roundtable: Design for Manufacturability.
IEEE Des. Test Comput., 2004

Test at Gbps: Megaproblem or micromanagement?
IEEE Des. Test Comput., 2004

Redundancy & It's Not Just for Defects Anymore.
Proceedings of the 12th IEEE International Workshop on Memory Technology, 2004

A Modular Wrapper Enabling High Speed BIST and Repair for Small Wide Memories.
Proceedings of the Proceedings 2004 International Test Conference (ITC 2004), 2004

From Working Design Flow to Working Chips: Dependencies and Impacts of Methodology Decisions.
Proceedings of the 2004 Design, 2004

2003
ITC Highlights.
IEEE Des. Test Comput., 2003

ITC 2003: Breaking Test Interface Bottlenecks.
IEEE Des. Test Comput., 2003

Guest editorial - testing and verification of communication system-on-chip devices.
IEEE Commun. Mag., 2003

Applying Defect-Based Test to Embedded Memories in a COT Model.
Proceedings of the 11th IEEE International Workshop on Memory Technology, 2003

Silicon IP And Successful DFM.
Proceedings of the Proceedings 2003 International Test Conference (ITC 2003), Breaking Test Interface Bottlenecks, 28 September, 2003

DFM: The Real 90nm Hurdle.
Proceedings of the Proceedings 2003 International Test Conference (ITC 2003), Breaking Test Interface Bottlenecks, 28 September, 2003

Redundancy, Repair, and Test Features of a 90nm Embedded SRAM Generator.
Proceedings of the 18th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2003), 2003

2002
Guest Editors' Introduction: Stressing the Fundamentals.
IEEE Des. Test Comput., 2002

Test as a Key Enabler for Faster Yield Ramp-Up.
Proceedings of the 20th IEEE VLSI Test Symposium (VTS 2002), Without Testing It's a Gamble, 28 April, 2002

Wireless Test.
Proceedings of the 20th IEEE VLSI Test Symposium (VTS 2002), Without Testing It's a Gamble, 28 April, 2002

Test Generation and Fault Modeling for Stress Testing (invited).
Proceedings of the 3rd International Symposium on Quality of Electronic Design, 2002

2000
Current ratios: a self-scaling technique for production IDDQ testing.
Proceedings of the Proceedings IEEE International Test Conference 2000, 2000

1999
Nanometer Technology Effects on Fault Models for IC Testing.
Computer, 1999

Extending the Pseudo-Stuck-At Fault Model to Provide Complete IDDQ Coverage.
Proceedings of the 17th IEEE VLSI Test Symposium (VTS '99), 1999

Current ratios: a self-scaling technique for production I_DDQ testing.
Proceedings of the Proceedings IEEE International Test Conference 1999, 1999

Trends in SLI design and their effect on test.
Proceedings of the Proceedings IEEE International Test Conference 1999, 1999

It Makes Sense to Combine DFT and DFR/DFY.
Proceedings of the Proceedings IEEE International Test Conference 1999, 1999

1998
On-chip versus off-chip test: an artificial dichotomy.
Proceedings of the Proceedings IEEE International Test Conference 1998, 1998

How will CAD handle billion-transistor systems? (panel).
Proceedings of the 1998 IEEE/ACM International Conference on Computer-Aided Design, 1998

1997
Modeling the Unmodelable: Algorithmic Fault Diagnosis.
IEEE Des. Test Comput., 1997

An experimental study comparing the relative effectiveness of functional, scan, IDDq and delay-fault testing.
Proceedings of the 15th IEEE VLSI Test Symposium (VTS'97), 1997

Power Dissipation During Testing: Should We Worry About it?
Proceedings of the 15th IEEE VLSI Test Symposium (VTS'97), 1997

So What Is an Optimal Test Mix? A Discussion of the SEMATECH Methods Experiment.
Proceedings of the Proceedings IEEE International Test Conference 1997, 1997

1996
When tools cry wolf: Testability pitfalls of synthesized designs.
IEEE Des. Test Comput., 1996

Volume Manufacturing - ICs and Boards: DFT to the Rescue?
Proceedings of the 14th IEEE VLSI Test Symposium (VTS'96), April 28, 1996

I<sub>DDQ</sub> and AC Scan: The War Against Unmodelled Defects.
Proceedings of the Proceedings IEEE International Test Conference 1996, 1996

Modelling the Unmodellable: Algorithmic Fault Diagnosis.
Proceedings of the Proceedings IEEE International Test Conference 1996, 1996

1995
An Overview of Test Synthesis Tools.
IEEE Des. Test Comput., 1995

Finding Defects with Fault Models.
Proceedings of the Proceedings IEEE International Test Conference 1995, 1995

1994
The Effect on Quality of Non-Uniform Fault Coverage and Fault Probability.
Proceedings of the Proceedings IEEE International Test Conference 1994, 1994

1993
Test Sets and Reject Rates: All Fault Coverages are Not Created Equal.
IEEE Des. Test Comput., 1993

Biased Voting: A Method for Simulating CMOS Bridging Faults in the Presence of Variable Gate Logic.
Proceedings of the Proceedings IEEE International Test Conference 1993, Designing, Testing, and Diagnostics, 1993

BP-1992 A Comparison of Defect Models for Fault Location with I<sub>DDQ</sub> Measurements.
Proceedings of the Proceedings IEEE International Test Conference 1993, Designing, Testing, and Diagnostics, 1993

1992
Using an asymmetric error model to study aliasing in signature analysis registers.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1992

IDDQ testing as a component of a test suite: The need for several fault coverage metrics.
J. Electron. Test., 1992

Diagnosis of leakage faults with IDDQ.
J. Electron. Test., 1992

The Effectiveness of I<sub>DDQ</sub>, Functional and Scan Tests: How Many Fault Coverages Do We Need?
Proceedings of the Proceedings IEEE International Test Conference 1992, 1992

A Comparison of Defect Models for Fault Location with I<sub>DDQ</sub> Measurements.
Proceedings of the Proceedings IEEE International Test Conference 1992, 1992

1991
The Effect of Different Test Sets on Quality Level Prediction: When is 80% better than 90%?
Proceedings of the Proceedings IEEE International Test Conference 1991, 1991

Fault Location with Current Monitoring.
Proceedings of the Proceedings IEEE International Test Conference 1991, 1991

1989
: Experiments on Aliasing in Signature Analysis Registers.
Proceedings of the Proceedings International Test Conference 1989, 1989

A diagnosis method using pseudo-random vectors without intermediate signatures.
Proceedings of the 1989 IEEE International Conference on Computer-Aided Design, 1989

1988
Aliasing probability of non-exhaustive randomized syndrome tests.
Proceedings of the 1988 IEEE International Conference on Computer-Aided Design, 1988


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