Kaijie Wei

Orcid: 0000-0002-3782-2177

According to our database1, Kaijie Wei authored at least 16 papers between 2018 and 2023.

Collaborative distances:

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Dataset
Other 

Links

On csauthors.net:

Bibliography

2023
RT-libSGM: FPGA-Oriented Real-Time Stereo Matching System with High Scalability.
IEICE Trans. Inf. Syst., March, 2023

A cost/power efficient storage system with directly connected FPGA and SATA disks.
Proceedings of the 16th IEEE International Symposium on Embedded Multicore/Many-core Systems-on-Chip, 2023

A state vector quantum simulator working on FPGAs with extensible SATA storage.
Proceedings of the International Conference on Field Programmable Technology, 2023

Enormous-Scale Quantum State Vector Calculation with FPGA-accelerated SATA storages.
Proceedings of the International Conference on Field Programmable Technology, 2023

Low power implementation of Geometric High-order Decorrelation-based Source Separation on an FPGA board.
Proceedings of the IEEE Symposium in Low-Power and High-Speed Chips, 2023

2022
Weighted Least Square Filter for Improving the Quality of Depth Map on FPGA.
Int. J. Netw. Comput., 2022

Multi-board FPGA Implementation to Solve the Satisfiability Problem for Multi-Agent Path Finding in Smart Factory.
Proceedings of the 2022 Tenth International Symposium on Computing and Networking, CANDAR 2022, 2022

An FPGA off-loading of HARK sound source localization.
Proceedings of the 2022 Tenth International Symposium on Computing and Networking, CANDAR 2022, 2022

An Implementation of a 3D Image Filter for Motion Vector Generation on an FPGA Board.
Proceedings of the Tenth International Symposium on Computing and Networking, 2022

RT-libSGM: An Implementation of a Real-time Stereo Matching System on FPGA.
Proceedings of the HEART 2022: International Symposium on Highly-Efficient Accelerators and Reconfigurable Technologies, Tsukuba, Japan, June 9, 2022

2021
An implementation methodology for Neural Network on a Low-end FPGA Board.
Int. J. Netw. Comput., 2021

CLAHE Implementation and Evaluation on a Low-End FPGA Board by High-Level Synthesis.
IEICE Trans. Inf. Syst., 2021

Weight Least Square Filter for Improving the Quality of Depth Map on FPGA.
Proceedings of the Ninth International Symposium on Computing and Networking, 2021

2020
CLAHE implementation on a low-end FPGA board by high-level synthesis.
Proceedings of the Eighth International Symposium on Computing and Networking Workshops, 2020

2019
FPGA/Python Co-Design for Lane Line Detection on a PYNQ-Z1 Board.
Proceedings of the 13th IEEE International Symposium on Embedded Multicore/Many-core Systems-on-Chip, 2019

2018
FPGA Design for Autonomous Vehicle Driving Using Binarized Neural Networks.
Proceedings of the International Conference on Field-Programmable Technology, 2018


  Loading...