Katsushi Asahina

According to our database1, Katsushi Asahina authored at least 4 papers between 2008 and 2011.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Dataset
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Links

On csauthors.net:

Bibliography

2011
An 80Gb/s dependable communication SoC with PCI express I/F and 8 CPUs.
Proceedings of the IEEE International Solid-State Circuits Conference, 2011

An 80 Gbps dependable multicore communication SoC with PCI express I/F and intelligent interrupt controller.
Proceedings of the 2011 IEEE Symposium on Low-Power and High-Speed Chips, 2011

2009
Low-jitter fractional spread-spectrum clock generator using fast-settling dual charge-pump technique for Serial-ATA application.
Proceedings of the 35th European Solid-State Circuits Conference, 2009

2008
A 6Gb/s RX Equalizer Adapted Using Direct Measurement of the Equalizer Output Amplitude.
Proceedings of the 2008 IEEE International Solid-State Circuits Conference, 2008


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