Yasushi Hayakawa

According to our database, Yasushi Hayakawa authored at least 3 papers between 1998 and 2011.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2011

An 80Gb/s dependable communication SoC with PCI express I/F and 8 CPUs.

Sugako Otani, Hiroyuki Kondo, Itaru Nonomura, Atsuyuki Ikeya, Minoru Uemura, Yasushi Hayakawa, Takeshi Oshita, Satoshi Kaneko, Katsushi Asahina, Kazutami Arimoto, Shin'ichi Miura, Toshihiro Hanawa, Taisuke Boku, Mitsuhisa Sato

Proceedings of the IEEE International Solid-State Circuits Conference, 2011

2008

A 6Gb/s RX Equalizer Adapted Using Direct Measurement of the Equalizer Output Amplitude.

H. Uchiki, Y. Ota, M. Tani, Yasushi Hayakawa, Katsushi Asahina

Proceedings of the 2008 IEEE International Solid-State Circuits Conference, 2008

1998

A low power SRAM using auto-backgate-controlled MT-CMOS.

Koji Nii, Hiroshi Makino, Yoshiki Tsujihashi, Chikayoshi Morishima, Yasushi Hayakawa, Hiroyuki Nunogami, Takahiko Arakawa, Hisanori Hamano

Proceedings of the 1998 International Symposium on Low Power Electronics and Design, 1998