Kaveh Aasaraai

Orcid: 0000-0002-9139-7861

According to our database1, Kaveh Aasaraai authored at least 19 papers between 2006 and 2023.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

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Links

On csauthors.net:

Bibliography

2023
Cyclone-NTT: An NTT/FFT Architecture Using Quasi-Streaming of Large Datasets on DDR- and HBM-based FPGA Platforms.
Proceedings of the 2023 ACM/SIGDA International Symposium on Field Programmable Gate Arrays, 2023

2022
CycloneNTT: An NTT/FFT Architecture Using Quasi-Streaming of Large Datasets on DDR- and HBM-based FPGA Platforms.
IACR Cryptol. ePrint Arch., 2022

FPGA Acceleration of Multi-Scalar Multiplication: CycloneMSM.
IACR Cryptol. ePrint Arch., 2022

2018
RAW 2018 Invited Talks.
Proceedings of the 2018 IEEE International Parallel and Distributed Processing Symposium Workshops, 2018

2014
What limits the operating frequency of a soft processor design.
Proceedings of the 2014 International Conference on ReConFigurable Computing and FPGAs, 2014

An Architectural Approach to Characterizing and Eliminating Sources of Inefficiency in a Soft Processor Design.
Proceedings of the 22nd IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2014

2013
Low-cost, high-performance branch predictors for soft processors.
Proceedings of the 23rd International Conference on Field programmable Logic and Applications, 2013

2012
NCOR: An FPGA-Friendly Nonblocking Data Cache for Soft Processors with Runahead Execution.
Int. J. Reconfigurable Comput., 2012

SPREX: A soft processor with Runahead execution.
Proceedings of the 2012 International Conference on Reconfigurable Computing and FPGAs, 2012

Toward virtualizing branch direction prediction.
Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012

2010
Caliper: a tool to generate precise and closed-loop traffic.
Proceedings of the ACM SIGCOMM 2010 Conference on Applications, 2010

An Efficient Non-blocking Data Cache for Soft Processors.
Proceedings of the ReConFig'10: 2010 International Conference on Reconfigurable Computing and FPGAs, 2010

Design space exploration of instruction schedulers for out-of-order soft processors.
Proceedings of the International Conference on Field-Programmable Technology, 2010

2009
Towards a viable out-of-order soft core: Copy-Free, checkpointed register renaming.
Proceedings of the 19th International Conference on Field Programmable Logic and Applications, 2009

2007
Exploiting Speculation Cost Prediction in Power-Aware Applications.
J. Low Power Electron., 2007

Speculative supplier identification for reducing power of interconnects in snoopy cache coherence protocols.
Proceedings of the 4th Conference on Computing Frontiers, 2007

Computational and storage power optimizations for the O-GEHL branch predictor.
Proceedings of the 4th Conference on Computing Frontiers, 2007

A Power-Aware Alternative for the Perceptron Branch Predictor.
Proceedings of the Advances in Computer Systems Architecture, 2007

2006
Low-Power Perceptron Branch Predictor.
J. Low Power Electron., 2006


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