Derek Chiou

According to our database1, Derek Chiou authored at least 65 papers between 1993 and 2019.

Collaborative distances:



In proceedings 
PhD thesis 




FlexSaaS: A Reconfigurable Accelerator for Web Search Selection.
TRETS, 2019

Dark Wires and the Opportunities for Reconfigurable Logic.
Computer Architecture Letters, 2019

Direct Universal Access: Making Data Center Resources Available to FPGA.
Proceedings of the 16th USENIX Symposium on Networked Systems Design and Implementation, 2019

Serving DNNs in Real Time at Datacenter Scale with Project Brainwave.
IEEE Micro, 2018

RAW 2018 Invited Talks.
Proceedings of the 2018 IEEE International Parallel and Distributed Processing Symposium Workshops, 2018

Minnow: Lightweight Offload Engines for Worklist Management and Worklist-Directed Prefetching.
Proceedings of the Twenty-Third International Conference on Architectural Support for Programming Languages and Operating Systems, 2018

FPGAs versus GPUs in Data centers.
IEEE Micro, 2017

Configurable Clouds.
IEEE Micro, 2017

Worklist-Directed Prefetching.
Computer Architecture Letters, 2017

HGum: Messaging framework for hardware accelerators.
Proceedings of the International Conference on ReConFigurable Computing and FPGAs, 2017

The microsoft catapult project.
Proceedings of the 2017 IEEE International Symposium on Workload Characterization, 2017

FPGA-Accelerated Transactional Execution of Graph Workloads.
Proceedings of the 2017 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2017

Introduction to Special Issue on Reconfigurable Components with Source Code.
TRETS, 2016

Impact of Future Technologies on Architecture.
IEEE Micro, 2016

Proprietary versus Open Instruction Sets.
IEEE Micro, 2016

An interview with Yale Patt.
Commun. ACM, 2016

A cloud-scale acceleration architecture.
Proceedings of the 49th Annual IEEE/ACM International Symposium on Microarchitecture, 2016

Heterogeneous Computing and Infrastructure for Energy Efficiency in Microsoft Data Centers: Extended Abstract.
Proceedings of the 2016 International Symposium on Low Power Electronics and Design, 2016

HGum: Messaging Framework for Hardware Accelerators (Abstact Only).
Proceedings of the 2016 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2016

Intel Acquires Altera: How Will the World of FPGAs be Affected?
Proceedings of the 2016 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2016

Guest Editorial: SBAC-PAD 2013.
International Journal of Parallel Programming, 2015

Keynote talk II: Accelerating data centers using reconfigurable logic.
Proceedings of the 13. ACM/IEEE International Conference on Formal Methods and Models for Codesign, 2015

GPGPU performance and power estimation using machine learning.
Proceedings of the 21st IEEE International Symposium on High Performance Computer Architecture, 2015

Growing a Healthy FPGA Ecosystem.
Proceedings of the 2015 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2015

Accelerating data centers with reconfigurable logic.
Proceedings of the 26th IEEE International Conference on Application-specific Systems, 2015

FPGA-Accelerated Simulation of Computer Systems
Synthesis Lectures on Computer Architecture, Morgan & Claypool Publishers, 2014

A reconfigurable fabric for accelerating large-scale datacenter services.
Proceedings of the ACM/IEEE 41st International Symposium on Computer Architecture, 2014

Cryptoraptor: high throughput reconfigurable cryptographic processor.
Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2014

Hardware and Software Implementations of Prim's Algorithm for Efficient Minimum Spanning Tree Computation.
Proceedings of the Embedded Systems: Design, Analysis and Verification, 2013

An FPGA-based in-line accelerator for Memcached.
Proceedings of the 2013 IEEE Hot Chips 25 Symposium (HCS), 2013

Implementing microprocessors from simplified descriptions.
Proceedings of the 18th Asia and South Pacific Design Automation Conference, 2013

Compiling high throughput network processors.
Proceedings of the ACM/SIGDA 20th International Symposium on Field Programmable Gate Arrays, 2012

On the asymptotic costs of multiplexer-based reconfigurability.
Proceedings of the 49th Annual Design Automation Conference 2012, 2012

MEMOCODE 2011 Hardware/Software CoDesign Contest: NoC simulator.
Proceedings of the 9th IEEE/ACM International Conference on Formal Methods and Models for Codesign, 2011

Enforcing architectural contracts in high-level synthesis.
Proceedings of the 48th Design Automation Conference, 2011

The Future of Architectural Simulation.
IEEE Micro, 2010

Programming Multicores: Do Applications Programmers Need to Write Explicitly Parallel Programs?
IEEE Micro, 2010

PrEsto: An FPGA-accelerated Power Estimation Methodology for Complex Systems.
Proceedings of the International Conference on Field Programmable Logic and Applications, 2010

NIFD: Non-intrusive FPGA Debugger -- Debugging FPGA 'Threads' for Rapid HW/SW Systems Prototyping.
Proceedings of the International Conference on Field Programmable Logic and Applications, 2010

A Framework for Packet Selection and Reporting.
RFC, March, 2009

Accurate Functional-First Multicore Simulators.
Computer Architecture Letters, 2009

QUICK: A flexible full-system functional model.
Proceedings of the IEEE International Symposium on Performance Analysis of Systems and Software, 2009

Soft connections: addressing the hardware-design modularity problem.
Proceedings of the 46th Design Automation Conference, 2009

Parallelizing computer system simulators.
Proceedings of the 22nd IEEE International Symposium on Parallel and Distributed Processing, 2008

RAMP: Research Accelerator for Multiple Processors.
IEEE Micro, 2007

Low-Power Design and Temperature Management.
IEEE Micro, 2007

Where Does Security Stand? New Vulnerabilities vs. Trusted Computing.
IEEE Micro, 2007

Reliability: Fallacy or Reality?
IEEE Micro, 2007

Single-Threaded vs. Multithreaded: Where Should We Focus?
IEEE Micro, 2007

Early Models for System-Level Power Estimation.
Proceedings of the Eighth International Workshop on Microprocessor Test and Verification (MTV 2007), 2007

FPGA-Accelerated Simulation Technologies (FAST): Fast, Full-System, Cycle-Accurate Simulators.
Proceedings of the 40th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO-40 2007), 2007

The FAST methodology for high-speed SoC/computer simulation.
Proceedings of the 2007 International Conference on Computer-Aided Design, 2007

The Network Processing Forum switch fabric benchmark specifications: an overview.
IEEE Network, 2005

Switch Fabric Interfaces.
IEEE Computer, 2003

Micro-Architectures of High Performance, Multi-User System Area Network Interface Cards.
Proceedings of the 14th International Parallel & Distributed Processing Symposium (IPDPS'00), 2000

Application-specific memory management for embedded systems using software-controlled caches.
Proceedings of the 37th Conference on Design Automation, 2000

Extending the reach of microprocessors: column and curious caching.
PhD thesis, 1999

StarT-Voyager: A Flexible Platform for Exploring Scalable SMP Issues.
Proceedings of the ACM/IEEE Conference on Supercomputing, 1998

Message passing support on StarT-Voyager.
Proceedings of the 5th International Conference On High Performance Computing, 1998

The StarT-Voyager Parallel System.
Proceedings of the 1998 International Conference on Parallel Architectures and Compilation Techniques, 1998

START-NG: Delivering Seamless Parallel Computing.
Proceedings of the Euro-Par '95 Parallel Processing, 1995

Performance Visualization on Monsoon.
J. Parallel Distrib. Comput., 1993

Performance Studies of Id on the Monsoon Dataflow System.
J. Parallel Distrib. Comput., 1993