Amirali Baniasadi

Microprocess. Microsystems, June, 2023

PDR-CapsNet: an Energy-Efficient Parallel Approach to Dynamic Routing in Capsule Networks.

[BibT_eX]

[DOI]

Samaneh Javadinia

CoRR, 2023

DSP: A Deep Neural Network Approach for Serving Cell Positioning in Mobile Networks.

[BibT_eX]

[DOI]

Proceedings of the 10th International Conference on Wireless Networks and Mobile Communications, 2023

Automatic Modulation Classification for NLOS 5G Signals with Deep Learning Approaches.

[BibT_eX]

[DOI]

Proceedings of the 10th International Conference on Wireless Networks and Mobile Communications, 2023

DeepCaps+: A Light Variant of DeepCaps.

[BibT_eX]

[DOI]

Proceedings of the 18th International Joint Conference on Computer Vision, 2023

EFL-Net: An Efficient Lightweight Neural Network Architecture for Retinal Vessel Segmentation.

[BibT_eX]

[DOI]

Nasrin Akbari

Proceedings of the 18th International Joint Conference on Computer Vision, 2023

IODnet: Indoor/Outdoor Telecommunication Signal Detection through Deep Neural Network.

[BibT_eX]

[DOI]

Proceedings of the 16th IEEE International Symposium on Embedded Multicore/Many-core Systems-on-Chip, 2023

Detection of COVID-19 Cases from X-ray Images Using Capsule-based Network.

[BibT_eX]

[DOI]

Donya Ashtiani Haghighi

Proceedings of the International Conference on Multimedia Computing, 2023

Dark Web Traffic Detection Using Supervised Machine Learning.

[BibT_eX]

[DOI]

Sahra Zangeneh Nezhad

Proceedings of the IEEE Canadian Conference on Electrical and Computer Engineering, 2023

Blockchain-Based, Privacy-Preserving, First Price Sealed Bid Auction (FPSBA) Verifiable by Participants.

[BibT_eX]

[DOI]

Ehsan Ghasaei

Proceedings of the 5th Conference on Blockchain Research & Applications for Innovative Networks and Services, 2023

2022

Convolutional Fully-Connected Capsule Network (CFC-CapsNet): A Novel and Fast Capsule Network.

[BibT_eX]

[DOI]

J. Signal Process. Syst., 2022

Turn-aware Application Mapping using Reinforcement Learning in Power Gating-enabled Network on Chip.

[BibT_eX]

[DOI]

Mohammadmehdi Shammasi

Mohammad Baharloo

Meisam Abdollahi

Proceedings of the 15th IEEE International Symposium on Embedded Multicore/Many-core Systems-on-Chip, 2022

DL-CapsNet: A Deep and Light Capsule Network.

[BibT_eX]

[DOI]

Proceedings of the Design and Architecture for Signal and Image Processing, 2022

An Enhanced (Margin-based) Quantum Annealing Approach to Phase-Unwrap SAR Images.

[BibT_eX]

[DOI]

Khaled A. Helal Kelany

Clemens P. J. Adolphs

Proceedings of the IEEE Canadian Conference on Electrical and Computer Engineering, 2022

2021

LE-CapsNet: A Light and Enhanced Capsule Network.

[BibT_eX]

[DOI]

Proceedings of the 20th IEEE International Conference on Machine Learning and Applications, 2021

PrunedCaps: A Case For Primary Capsules Discrimination.

[BibT_eX]

[DOI]

Ramin Sharifi

Proceedings of the 20th IEEE International Conference on Machine Learning and Applications, 2021

Convolutional Fully-Connected Capsule Network (CFC-CapsNet).

[BibT_eX]

[DOI]

Proceedings of the DASIP '21: Workshop on Design and Architectures for Signal and Image Processing (14th edition), 2021

2020

Energy Efficient On-Demand Dynamic Branch Prediction Models.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 2020

Quantum Annealing Approaches to the Phase-Unwrapping Problem in Synthetic-Aperture Radar Imaging.

[BibT_eX]

[DOI]

Khaled A. Helal Kelany

Clemens P. J. Adolphs

Bardia Barabadi

Proceedings of the IEEE International Conference on Quantum Computing and Engineering, 2020

Improving InSAR Image Quality and Co-Registration through CNN-Based Super-Resolution.

[BibT_eX]

[DOI]

Khaled A. Helal Kelany

Matthew Gara

Proceedings of the IEEE International Symposium on Circuits and Systems, 2020

Zero-skipping in CapsNet. Is it worth it?

[BibT_eX]

[DOI]

Ramin Sharifi

Proceedings of 35th International Conference on Computers and Their Applications, 2020

Quick-CapsNet (QCN): A Fast Alternative to Capsule Networks.

[BibT_eX]

[DOI]

Ramin Sharifi

Proceedings of the 17th IEEE/ACS International Conference on Computer Systems and Applications, 2020

2019

Multiobjective GPU design space exploration optimization.

[BibT_eX]

[DOI]

Microprocess. Microsystems, 2019

Efficient implementation of OpenACC cache directive on NVIDIA GPUs.

[BibT_eX]

[DOI]

Int. J. High Perform. Comput. Netw., 2019

Dual-Stage Phase Unwrapping.

[BibT_eX]

[DOI]

Proceedings of the 2019 IEEE Nordic Circuits and Systems Conference, 2019

Scale Invariant Super-Resolutions Methods with Application to InSAR Images.

[BibT_eX]

[DOI]

Proceedings of the 2019 IEEE Asia Pacific Conference on Circuits and Systems, 2019

2018

TELEPORT: Hardware/software alternative to CUDA shared memory programming.

[BibT_eX]

[DOI]

Microprocess. Microsystems, 2018

Loop Perforation in OpenACC.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Conference on Parallel & Distributed Processing with Applications, 2018

2017

Optimum Power-Performance GPU Configuration Prediction Based on Code Attributes.

[BibT_eX]

[DOI]

Proceedings of the 2017 International Conference on High Performance Computing & Simulation, 2017

2016

Employing Software-Managed Caches in OpenACC: Opportunities and Benefits.

[BibT_eX]

[DOI]

ACM Trans. Model. Perform. Evaluation Comput. Syst., 2016

OpenACC Cache Directive: Opportunities and Optimizations.

[BibT_eX]

[DOI]

Proceedings of the Third Workshop on Accelerator Programming Using Directives, 2016

Employing Compression Solutions under OpenACC.

[BibT_eX]

[DOI]

Ebad Salehi

Proceedings of the 2016 IEEE International Parallel and Distributed Processing Symposium Workshops, 2016

2015

Power-efficient prefetching on GPGPUs.

[BibT_eX]

[DOI]

J. Supercomput., 2015

A Case Study in Reverse Engineering GPGPUs: Outstanding Memory Handling Resources.

[BibT_eX]

[DOI]

Ebad Salehi

SIGARCH Comput. Archit. News, 2015

GPU design space exploration: NN-based models.

[BibT_eX]

[DOI]

Proceedings of the IEEE Pacific Rim Conference on Communications, 2015

Rethinking Prefetching in GPGPUs: Exploiting Unique Opportunities.

[BibT_eX]

[DOI]

Proceedings of the 17th IEEE International Conference on High Performance Computing and Communications, 2015

2014

HARP: Harnessing inactive threads in many-core processors.

[BibT_eX]

[DOI]

Mohammad Hossein Hajkazemi

ACM Trans. Embed. Comput. Syst., 2014

CEDAR: Modeling impact of component error derating and read frequency on system-level vulnerability in high-performance processors.

[BibT_eX]

[DOI]

Microelectron. Reliab., 2014

An Alternative Hybrid Power-Aware Adder for High-Performance Processors.

[BibT_eX]

[DOI]

J. Low Power Electron., 2014

Column selection solutions for L1 data caches implemented using eight-transistor cells.

[BibT_eX]

[DOI]

IET Comput. Digit. Tech., 2014

IPMACC: Open Source OpenACC to CUDA/OpenCL Translator.

[BibT_eX]

[DOI]

Alireza Majidi

CoRR, 2014

A case against small data types in GPGPUs.

[BibT_eX]

[DOI]

Proceedings of the IEEE 25th International Conference on Application-Specific Systems, 2014

2013

ARV-ALA: Improving performance of software transactional memory through adaptive read and write policies.

[BibT_eX]

[DOI]

Yvonne Coady

Sci. Comput. Program., 2013

Towards green GPUs: Warp size impact analysis.

[BibT_eX]

[DOI]

Proceedings of the International Green Computing Conference, 2013

Application Specific Low Leakage data Cache for embedded processors.

[BibT_eX]

[DOI]

Fatemeh Eslami

Proceedings of the International Green Computing Conference, 2013

Using synchronization stalls in power-aware accelerators.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation and Test in Europe, 2013

Warp size impact in GPUs: large or small?

[BibT_eX]

[DOI]

Mohammad Hossein Hajkazemi

Proceedings of the 6th Workshop on General Purpose Processor Using Graphics Processing Units, 2013

FARHAD: A Fault-Tolerant Power-Aware Hybrid Adder for add intensive applications.

[BibT_eX]

[DOI]

Hossein Asadi

Proceedings of the 24th International Conference on Application-Specific Systems, 2013

Inter-warp Instruction Temporal Locality in Deep-Multithreaded GPUs.

[BibT_eX]

[DOI]

Proceedings of the Architecture of Computing Systems - ARCS 2013, 2013

2012

Heterogeneous Interconnect for Low-Power Snoop-Based Chip Multiprocessors.

[BibT_eX]

[DOI]

Narges Shahidi

Ali Shafiee

J. Low Power Electron., 2012

Leakage-Aware Speculative Branch Target Buffer.

[BibT_eX]

[DOI]

Saman Khoshbakht

J. Low Power Electron., 2012

Dynamic Warp Resizing in High-Performance SIMT

[BibT_eX]

[DOI]

CoRR, 2012

Investigating Warp Size Impact in GPUs

[BibT_eX]

[DOI]

CoRR, 2012

Performance and Power Solutions for Caches Using 8T SRAM Cells.

[BibT_eX]

[DOI]

Proceedings of the 45th Annual IEEE/ACM International Symposium on Microarchitecture, 2012

Dynamic warp resizing: Analysis and benefits in high-performance SIMT.

[BibT_eX]

[DOI]

Proceedings of the 30th International IEEE Conference on Computer Design, 2012

Efficient Design Space Exploration of GPGPU Architectures.

[BibT_eX]

[DOI]

Nikitas J. Dimopoulos

Proceedings of the Euro-Par 2012: Parallel Processing Workshops, 2012

2011

History-aware, resource-based dynamic scheduling for heterogeneous multi-core processors.

[BibT_eX]

[DOI]

A. Zolfaghari Jooya

M. Analoui

IET Comput. Digit. Tech., 2011

Using Silent Writes in Low-Power Traffic-Aware ECC.

[BibT_eX]

[DOI]

Mostafa Kishani

Hossein Pedram

Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, Optimization, and Simulation, 2011

Power and frequency analysis for data and control independence in embedded processors.

[BibT_eX]

[DOI]

Farzad Samie

Proceedings of the 2011 International Green Computing Conference and Workshops, 2011

Instruction and data cache peak temperature reduction using cache access balancing in embedded processors.

[BibT_eX]

[DOI]

Mohsen Taherian

Hamid Noori

Proceedings of the 9th IEEE/ACS International Conference on Computer Systems and Applications, 2011

2010

Power-aware BTB for modern processors.

[BibT_eX]

[DOI]

Comput. Electr. Eng., 2010

System-Level Vulnerability Estimation for Data Caches.

[BibT_eX]

[DOI]

Alireza Haghdoost

Hossein Asadi

Proceedings of the 16th IEEE Pacific Rim International Symposium on Dependable Computing, 2010

Using Partial Tag Comparison in Low-Power Snoop-Based Chip Multiprocessors.

[BibT_eX]

[DOI]

Ali Shafiee

Narges Shahidi

Proceedings of the Computer Architecture, 2010

Helia: Heterogeneous Interconnect for Low Resolution Cache Access in snoop-based chip multiprocessors.

[BibT_eX]

[DOI]

Ali Shafiee

Narges Shahidi

Proceedings of the 28th International Conference on Computer Design, 2010

Storage-Aware Value Prediction.

[BibT_eX]

[DOI]

Mohammad Salehi

Proceedings of the 13th Euromicro Conference on Digital System Design, 2010

2009

Power-aware scoreboard alternatives for multimedia processors.

[BibT_eX]

[DOI]

Babak Salamat

Microprocess. Microsystems, 2009

A New Cell Design Methodology for Balanced XOR-XNOR Circuits for Hybrid-CMOS Logic.

[BibT_eX]

[DOI]

J. Low Power Electron., 2009

Write Invalidation Analysis in Chip Multiprocessors.

[BibT_eX]

[DOI]

Newsha Ardalani

Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, 2009

Temperature reduction analysis in Sentry Tag cache systems.

[BibT_eX]

[DOI]

Proceedings of the 10th workshop on MEmory performance, 2009

Application Specific Transistor Sizing for Low Power Full Adders.

[BibT_eX]

[DOI]

Fatemeh Eslami

Proceedings of the 20th IEEE International Conference on Application-Specific Systems, 2009

2008

Using supplier locality in power-aware interconnects and caches in chip multiprocessors.

[BibT_eX]

[DOI]

J. Syst. Archit., 2008

Exploiting program cyclic behavior to reduce memory latency in embedded processors.

[BibT_eX]

[DOI]

Proceedings of the 2008 ACM Symposium on Applied Computing (SAC), 2008

Adaptive Read Validation in Time-Based Software Transactional Memory.

[BibT_eX]

[DOI]

Yvonne Coady

Proceedings of the Euro-Par 2008 Workshops, 2008

2007

Investigating cache energy and latency break-even points in high performance processors.

[BibT_eX]

[DOI]

SIGARCH Comput. Archit. News, 2007

Speculative trivialization point advancing in high-performance processors.

[BibT_eX]

[DOI]

J. Syst. Archit., 2007

Exploiting Speculation Cost Prediction in Power-Aware Applications.

[BibT_eX]

[DOI]

J. Low Power Electron., 2007

A Power-Aware Prediction-Based Cache Coherence Protocol for Chip Multiprocessors.

[BibT_eX]

[DOI]

Proceedings of the 21th International Parallel and Distributed Processing Symposium (IPDPS 2007), 2007

Speculative supplier identification for reducing power of interconnects in snoopy cache coherence protocols.

[BibT_eX]

[DOI]

Proceedings of the 4th Conference on Computing Frontiers, 2007

Computational and storage power optimizations for the O-GEHL branch predictor.

[BibT_eX]

[DOI]

Proceedings of the 4th Conference on Computing Frontiers, 2007

Exploiting Task Temperature Profiling in Temperature-Aware Task Scheduling for Computational Clusters.

[BibT_eX]

[DOI]

Daniel C. Vanderster

Nikitas J. Dimopoulos

Proceedings of the Advances in Computer Systems Architecture, 2007

A Power-Aware Alternative for the Perceptron Branch Predictor.

[BibT_eX]

[DOI]

Proceedings of the Advances in Computer Systems Architecture, 2007

2006

Low-Power Perceptron Branch Predictor.

[BibT_eX]

[DOI]

J. Low Power Electron., 2006

Area-Aware Optimizations for Resource Contrained Branch Predictors Exploited in Embedded Processors.

[BibT_eX]

[DOI]

Babak Salamat

Proceedings of 2006 International Conference on Embedded Computer Systems: Architectures, 2006

Reducing Execution Unit Leakage Power in Embedded Processors.

[BibT_eX]

[DOI]

Houman Homayoun

Proceedings of the Embedded Computer Systems: Architectures, 2006

Branchless cycle prediction for embedded processors.

[BibT_eX]

[DOI]

Proceedings of the 2006 ACM Symposium on Applied Computing (SAC), 2006

2005

Area-Aware Pipeline Gating for Embedded Processors.

[BibT_eX]

[DOI]

Babak Salamat

Proceedings of the Integrated Circuit and System Design, 2005

Improving Energy-Efficiency by Bypassing Trivial Computations.

[BibT_eX]

[DOI]

Proceedings of the 19th International Parallel and Distributed Processing Symposium (IPDPS 2005), 2005

Low-power prediction based data transfer architecture.

[BibT_eX]

[DOI]

Proceedings of the IEEE 2005 Custom Integrated Circuits Conference, 2005

Balancing clustering-induced stalls to improve performance in clustered processors.

[BibT_eX]

[DOI]

Proceedings of the Second Conference on Computing Frontiers, 2005

2004

SEPAS: a highly accurate energy-efficient branch predictor.

[BibT_eX]

[DOI]

Proceedings of the 2004 International Symposium on Low Power Electronics and Design, 2004

2003

Power-Aware Branch Predictor Update for High-Performance Processors.

[BibT_eX]

[DOI]

Proceedings of the Integrated Circuit and System Design, 2003

Back-End Dynamic Resource Allocation Heuristics for Power-Aware High-Performance Clustered Architectures.

[BibT_eX]

[DOI]

Proceedings of the 2003 Euromicro Symposium on Digital Systems Design (DSD 2003), 2003

2002

Asymmetric-frequency clustering: a power-aware back-end for high-performance processors.

[BibT_eX]

[DOI]

Proceedings of the 2002 International Symposium on Low Power Electronics and Design, 2002

Branch Predictor Prediction: A Power-Aware Branch Predictor for High-Performance Processors.

[BibT_eX]

[DOI]

Proceedings of the 20th International Conference on Computer Design (ICCD 2002), 2002

2001

Instruction flow-based front-end throttling for power-aware high-performance processors.

[BibT_eX]

[DOI]

Proceedings of the 2001 International Symposium on Low Power Electronics and Design, 2001

Slice-processors: an implementation of operation-based prediction.

[BibT_eX]

[DOI]

Dionisios N. Pnevmatikatos

Proceedings of the 15th international conference on Supercomputing, 2001

2000

Instruction distribution heuristics for quad-cluster, dynamically-scheduled, superscalar processors.

[BibT_eX]

[DOI]