Ke Wang

Orcid: 0000-0002-1956-5031

Affiliations:
  • University of Virginia, Department of Computer Science, Charlottesville, VA, USA


According to our database1, Ke Wang authored at least 20 papers between 2014 and 2019.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Bibliography

2019
MTTF Enhancement Power-C4 Bump Placement Optimization.
IEEE Trans. Very Large Scale Integr. Syst., 2019

2018
Hierarchical Pattern Mining with the Automata Processor.
Int. J. Parallel Program., 2018

2017
Accelerating Weeder: A DNA Motif Search Tool Using the Micron Automata Processor and FPGA.
IEICE Trans. Inf. Syst., 2017

Frequent subtree mining on the automata processor: challenges and opportunities.
Proceedings of the International Conference on Supercomputing, 2017

Pre-RTL Voltage and Power Optimization for Low-Cost, Thermally Challenged Multicore Chips.
Proceedings of the 2017 IEEE International Conference on Computer Design, 2017

2016
Tolerating the Consequences of Multiple EM-Induced C4 Bump Failures.
IEEE Trans. Very Large Scale Integr. Syst., 2016

ANMLzoo: a benchmark suite for exploring bottlenecks in automata processing engines and architectures.
Proceedings of the 2016 IEEE International Symposium on Workload Characterization, 2016

Generating efficient and high-quality pseudo-random behavior on Automata Processors.
Proceedings of the 34th IEEE International Conference on Computer Design, 2016

An overview of micron's automata processor.
Proceedings of the Eleventh IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis, 2016

Sequential pattern mining with the Micron automata processor.
Proceedings of the ACM International Conference on Computing Frontiers, CF'16, 2016

Entity resolution acceleration using the automata processor.
Proceedings of the 2016 IEEE International Conference on Big Data (IEEE BigData 2016), 2016

2015
Brill tagging on the Micron Automata Processor.
Proceedings of the 9th IEEE International Conference on Semantic Computing, 2015

Transient voltage noise in charge-recycled power delivery networks for many-layer 3D-IC.
Proceedings of the IEEE/ACM International Symposium on Low Power Electronics and Design, 2015

Association Rule Mining with the Micron Automata Processor.
Proceedings of the 2015 IEEE International Parallel and Distributed Processing Symposium, 2015

A cross-layer design exploration of charge-recycled power-delivery in many-layer 3d-IC.
Proceedings of the 52nd Annual Design Automation Conference, 2015

Regular expression acceleration on the micron automata processor: Brill tagging as a case study.
Proceedings of the 2015 IEEE International Conference on Big Data (IEEE BigData 2015), Santa Clara, CA, USA, October 29, 2015

2014
SPEC ACCEL: A Standard Application Suite for Measuring Hardware Accelerator Performance.
Proceedings of the High Performance Computing Systems. Performance Modeling, Benchmarking, and Simulation, 2014

Architecture implications of pads as a scarce resource.
Proceedings of the ACM/IEEE 41st International Symposium on Computer Architecture, 2014

Walking Pads: Managing C4 Placement for Transient Voltage Noise Minimization.
Proceedings of the 51st Annual Design Automation Conference 2014, 2014

Walking pads: Fast power-supply pad-placement optimization.
Proceedings of the 19th Asia and South Pacific Design Automation Conference, 2014


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