Kaushik Mazumdar

According to our database1, Kaushik Mazumdar authored at least 9 papers between 2012 and 2017.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Other 

Links

On csauthors.net:

Bibliography

2017
Pre-RTL Voltage and Power Optimization for Low-Cost, Thermally Challenged Multicore Chips.
Proceedings of the 2017 IEEE International Conference on Computer Design, 2017

2016
Enabling Wide Autonomous DVFS in a 22 nm Graphics Execution Core Using a Digitally Controlled Fully Integrated Voltage Regulator.
IEEE J. Solid State Circuits, 2016

2015
8.6 Enabling wide autonomous DVFS in a 22nm graphics execution core using a digitally controlled hybrid LDO/switched-capacitor VR with fast droop mitigation.
Proceedings of the 2015 IEEE International Solid-State Circuits Conference, 2015

A digitally-controlled power-aware low-dropout regulator to reduce standby current drain in ultra-low-power MCU.
Proceedings of the Sixteenth International Symposium on Quality Electronic Design, 2015

Transient voltage noise in charge-recycled power delivery networks for many-layer 3D-IC.
Proceedings of the IEEE/ACM International Symposium on Low Power Electronics and Design, 2015

A cross-layer design exploration of charge-recycled power-delivery in many-layer 3d-IC.
Proceedings of the 52nd Annual Design Automation Conference, 2015

2014
A multi-output on-chip switched-capacitor DC-DC converter for near- and sub-threshold power modes.
Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014

2012
Breaking the power delivery wall using voltage stacking.
Proceedings of the Great Lakes Symposium on VLSI 2012, 2012

Breaking the 3D IC power delivery wall.
Proceedings of the Conference Record of the Forty Sixth Asilomar Conference on Signals, 2012


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