Mohamed El-Hadedy

Orcid: 0000-0002-3823-0712

  • California State Polytechnic University, Department of Electrical and Computer Engineering, Pomona, USA

According to our database1, Mohamed El-Hadedy authored at least 33 papers between 2008 and 2023.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.



In proceedings 
PhD thesis 


Online presence:



RECO-ASCON: Reconfigurable ASCON hash functions for IoT applications.
Integr., November, 2023

BLTESTI: Benchmarking Lightweight TinyJAMBU on Embedded Systems for Trusted IoT.
Proceedings of the 36th IEEE International System-on-Chip Conference, 2023

RECO-LFSR: Reconfigurable Low-power Cryptographic processor based on LFSR for Trusted IoT platforms.
Proceedings of the 24th International Symposium on Quality Electronic Design, 2023

Agile-AES: Implementation of configurable AES primitive with agile design approach.
Integr., 2022

RECO-HCON: A High-Throughput Reconfigurable Compact ASCON Processor for Trusted IoT.
Proceedings of the 35th IEEE International System-on-Chip Conference, 2022

SHA-3-LPHP: Hardware Acceleration of SHA-3 for Low-Power High-Performance Systems.
Proceedings of the IEEE International Symposium on Software Reliability Engineering, 2021

Ensemble Hyperspectral Band Selection for Detecting Nitrogen Status in Grape Leaves.
Proceedings of the 19th IEEE International Conference on Machine Learning and Applications, 2020

Micro - GAGE: A Low-power Compact GAGE Hash Function Processor for IoT Applications.
Proceedings of the 27th IEEE International Conference on Electronics, Circuits and Systems, 2020

ASAP: Accelerated Short-Read Alignment on Programmable Hardware.
IEEE Trans. Computers, 2019

Reco-Pi: A reconfigurable Cryptoprocessor for π-Cipher.
J. Parallel Distributed Comput., 2019

Analysis and Modeling of Collaborative Execution Strategies for Heterogeneous CPU-FPGA Architectures.
Proceedings of the 2019 ACM/SPEC International Conference on Performance Engineering, 2019

Analysis and Optimization of I/O Cache Coherency Strategies for SoC-FPGA Device.
Proceedings of the 29th International Conference on Field Programmable Logic and Applications, 2019

Flexi-AES: A Highly-Parameterizable Cipher for a Wide Range of Design Constraints.
Proceedings of the 27th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2019

Triangle Counting and Truss Decomposition using FPGA.
Proceedings of the 2018 IEEE High Performance Extreme Computing Conference, 2018

Dual-Data Rate Transpose-Memory Architecture Improves the Performance, Power and Area of Signal-Processing Systems.
J. Signal Process. Syst., 2017

Accelerating Weeder: A DNA Motif Search Tool Using the Micron Automata Processor and FPGA.
IEICE Trans. Inf. Syst., 2017

On accelerating pair-HMM computations in programmable hardware.
Proceedings of the 27th International Conference on Field Programmable Logic and Applications, 2017

ASAP: Accelerated Short Read Alignment on Programmable Hardware (Abstract Only).
Proceedings of the 2017 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2017

PPE-ARX: Area- and power-efficient VLIW programmable processing element for IoT crypto-systems.
Proceedings of the 2017 NASA/ESA Conference on Adaptive Hardware and Systems, 2017

Posting with credibility in Micro-blogging systems using Digital Signatures and Watermarks: A case study on Twitter.
CoRR, 2016

A 16-Bit Reconfigurable Encryption Processor for p-Cipher.
Proceedings of the 2016 IEEE International Parallel and Distributed Processing Symposium Workshops, 2016

Generating efficient and high-quality pseudo-random behavior on Automata Processors.
Proceedings of the 34th IEEE International Conference on Computer Design, 2016

Hardware overhead analysis of programmability in ARX crypto processing.
Proceedings of the Fourth Workshop on Hardware and Architectural Support for Security and Privacy, 2015

π-Cipher: Authenticated Encryption for Big Data.
Proceedings of the Secure IT Systems - 19th Nordic Conference, NordSec 2014, Tromsø, 2014

Implementing Algorithms on FPGA Platforms.
PhD thesis, 2012

An Efficient Authorship Protection Scheme for Shared Multimedia Content.
Proceedings of the Sixth International Conference on Image and Graphics, 2011

Area efficient processing element architecture for compact hash functions systems on VIRTEX5 FPGA platform.
Proceedings of the 2011 NASA/ESA Conference on Adaptive Hardware and Systems, 2011

Single Core Implementation of Blue Midnight Wish Hash Function on VIRTEX 5 Platform.
IACR Cryptol. ePrint Arch., 2010

Implementing the Blue Midnight Wish Hash Function on Xilinx Virtex-5 FPGA Platform.
Proceedings of the ReConFig'10: 2010 International Conference on Reconfigurable Computing and FPGAs, 2010

Performance and area efficient transpose memory architecture for high throughput adaptive signal processing systems.
Proceedings of the 2010 NASA/ESA Conference on Adaptive Hardware and Systems, 2010

Resource-efficient implementation of Blue Midnight Wish-256 hash function on Xilinx FPGA platform.
Proceedings of the Sixth International Conference on Information Assurance and Security, 2010

Low Area Implementation of the Hash Function "Blue Midnight Wish 256" for FPGA Platforms.
Proceedings of the 1st International Conference on Intelligent Networking and Collaborative Systems, 2009

High Performance Implementation of a Public Key Block Cipher - MQQ, for FPGA Platforms.
IACR Cryptol. ePrint Arch., 2008