Keikichi Tamaru

According to our database, Keikichi Tamaru authored at least 29 papers between 1978 and 2000.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2000

A method for linking process-level variability to system performances.

Tomohiro Fujita, Ken-ichi Okada, Hiroaki Fujita, Hidetoshi Onodera, Keikichi Tamaru

Proceedings of ASP-DAC 2000, 2000

1999

A Practical Gate Resizing Technique Considering Glitch Reduction for Low Power Design.

Masanori Hashimoto, Hidetoshi Onodera, Keikichi Tamaru

Proceedings of the 36th Conference on Design Automation, 1999

1998

Model-adaptable MOSFET parameter-extraction method using an intermediate model.

Masaki Kondo, Hidetoshi Onodera, Keikichi Tamaru

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1998

A memory efficient array architecture for real-time motion estimation.

Vasily G. Moshnyaga, Naoto Watanabe, Keikichi Tamaru

Syst. Comput. Jpn., 1998

A power optimization method considering glitch reduction by gate sizing.

Masanori Hashimoto, Hidetoshi Onodera, Keikichi Tamaru

Proceedings of the 1998 International Symposium on Low Power Electronics and Design, 1998

Proposal of a timing model for CMOS logic gates driving a CRC load.

Akio Hirata, Hidetoshi Onodera, Keikichi Tamaru

Proceedings of the 1998 IEEE/ACM International Conference on Computer-Aided Design, 1998

Real time low bit-rate video coding algorithm using multi-stage hierarchical vector quantization.

Kazuhiko Terada, Masahiro Takeuchi, Kazutoshi Kobayashi, Keikichi Tamaru

Proceedings of the 1998 IEEE International Conference on Acoustics, 1998

A new architecture for in-memory image convolution.

Vasily G. Moshnyaga, Kazuhiro Suzuki, Keikichi Tamaru

Proceedings of the 1998 IEEE International Conference on Acoustics, 1998

1997

A Memory Efficient Array Architecture for Real-Time Motion Estimation.

Vasily G. Moshnyaga, Keikichi Tamaru

Proceedings of the 11th International Parallel Processing Symposium (IPPS '97), 1997

A memory efficient array architecture for full-search block matching algorithm.

Vasily G. Moshnyaga, Keikichi Tamaru

Proceedings of the 1997 IEEE International Conference on Acoustics, 1997

A current mode cyclic A/D converter with a 0.8 μm CMOS process.

Masaki Kondo, Hidetoshi Onodera, Keikichi Tamaru

Proceedings of the ASP-DAC '97 Asia and South Pacific Design Automation Conference, 1997

A functional memory type parallel processor for vector quantization.

Kazutoshi Kobayashi, Masayoshi Kinoshita, Masahiro Takeuchi, Hidetoshi Onodera, Keikichi Tamaru

Proceedings of the ASP-DAC '97 Asia and South Pacific Design Automation Conference, 1997

1996

Timing and Power Optimization by Gate Sizing Considering False Paths.

Guangqiu Chen, Hidetoshi Onodera, Keikichi Tamaru

Proceedings of the 6th Great Lakes Symposium on VLSI (GLS-VLSI '96), 1996

1995

High speed merged array multiplication.

Farhad Fuad Islam, Keikichi Tamaru

J. VLSI Signal Process., 1995

Register-Transfer Module Selection for Sub-Micron ASIC Design.

Vasily G. Moshnyaga, Yutaka Mori, Keikichi Tamaru

IEICE Trans. Inf. Syst., 1995

A Comparative Study of Switching Activity Reduction Techniques for Design of Low-Power Multipliers.

Vasily G. Moshnyaga, Keikichi Tamaru

Proceedings of the 1995 IEEE International Symposium on Circuits and Systems, ISCAS 1995, Seattle, Washington, USA, April 30, 1995

A New Algorithm for Sorting Problem with Reformed CAM.

Kuei-Ming Lu, Keikichi Tamaru

Proceedings of the 1995 IEEE International Symposium on Circuits and Systems, ISCAS 1995, Seattle, Washington, USA, April 30, 1995

An iterative gate sizing approach with accurate delay evaluation.

Guangqiu Chen, Hidetoshi Onodera, Keikichi Tamaru

Proceedings of the 1995 IEEE/ACM International Conference on Computer-Aided Design, 1995

A scheduling algorithm for synthesis of bus-partitioned architectures.

Vasily G. Moshnyaga, Fumiaki Ohbayashi, Keikichi Tamaru

Proceedings of the 1995 Conference on Asia Pacific Design Automation, Makuhari, Massa, Chiba, Japan, August 29, 1995

A model-adaptable MOSFET parameter extraction system.

Masaki Kondo, Hidetoshi Onodera, Keikichi Tamaru

Proceedings of the 1995 Conference on Asia Pacific Design Automation, Makuhari, Massa, Chiba, Japan, August 29, 1995

1994

Processing nested loop structure with data-flow dependence on a CAM-based processor HAPP.

Kuei-Ming Lu, Keikichi Tamaru

Proceedings of the International Symposium on Parallel Architectures, 1994

1993

An Architecture for Intermediate Area-time Complexity Multiplier.

Farhad Fuad Islam, Keikichi Tamaru

Proceedings of the 1993 IEEE International Symposium on Circuits and Systems, 1993

Layout-driven module selection for register-transfer synthesis of sub-micron ASIC's.

Vasily G. Moshnyaga, Hiroshi Mori, Hidetoshi Onodera, Keikichi Tamaru

Proceedings of the 1993 IEEE/ACM International Conference on Computer-Aided Design, 1993

High speed merged multiplication.

Farhad Fuad Islam, Keikichi Tamaru

Proceedings of the IEEE International Conference on Acoustics, 1993

1992

Design of data-path module generators from algorithmic representations.

Vasily G. Moshnyaga, Keikichi Tamaru, Hiroto Yasuura

Proceedings of the Synthesis for Control Dominated Circuits, 1992

1991

Branch-and-Bound Placement for Building Block Layout.

Hidetoshi Onodera, Yo Taniguchi, Keikichi Tamaru

Proceedings of the 28th Design Automation Conference, 1991

1990

Extraction of Functional Information from Combinatorial Circuits.

M. Ohmura, Hiroto Yasuura, Keikichi Tamaru

Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 1990

1987

System design of a special-purpose computer for LSI design rule checking.

Keikichi Tamaru, Hidetoshi Onodera

Syst. Comput. Jpn., 1987

1978

Development of a high-performance universal computing element - PULCE.

Hajime lizuka, Yutaka Hayashi, Keikichi Tamaru, Hisashi Hara

Proceedings of the American Federation of Information Processing Societies: 1978 National Computer Conference, 1978