Hidetoshi Onodera

According to our database1, Hidetoshi Onodera authored at least 184 papers between 1987 and 2019.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Awards

IEEE Fellow

IEEE Fellow 2018, "For contributions to variation-aware design and analysis of integrated circuits".

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Other 

Links

On csauthors.net:

Bibliography

2019
Circuit Techniques for Device-Circuit Interaction toward Minimum Energy Operation.
IPSJ Trans. System LSI Design Methodology, 2019

Area-efficient fully digital memory using minimum height standard cells for near-threshold voltage computing.
Integration, 2019

Impact of On-Chip Inductor and Power-Delivery-Network Stacking on Signal and Power Integrity.
IEICE Transactions, 2019

A Design Method of a Cell-Based Amplifier for Body Bias Generation.
IEICE Transactions, 2019

Analysis of Random Telegraph Noise (RTN) at Near-Threshold Operation by Measuring 154k Ring Oscillators.
Proceedings of the IEEE International Reliability Physics Symposium, 2019

NCTUcell: A DDA-Aware Cell Library Generator for FinFET Structure with Implicitly Adjustable Grid Map.
Proceedings of the 56th Annual Design Automation Conference 2019, 2019

BDD-based synthesis of optical logic circuits exploiting wavelength division multiplexing.
Proceedings of the 24th Asia and South Pacific Design Automation Conference, 2019

2018
Via-Switch FPGA: Highly Dense Mixed-Grained Reconfigurable Architecture With Overlay Via-Switch Crossbars.
IEEE Trans. VLSI Syst., 2018

Minimum Energy Point Tracking with All-Digital On-Chip Sensors.
J. Low Power Electronics, 2018

Design Methodology for Variation Tolerant D-Flip-Flop Using Regression Analysis.
IEICE Transactions, 2018

Sensor Signal Processing Using High-Level Synthesis With a Layered Architecture.
Embedded Systems Letters, 2018

Performance Modeling of VIA-Switch FPGA for Device-Circuit-Architecture Co-Optimization.
Proceedings of the 31st IEEE International System-on-Chip Conference, 2018

Maximizing Energy Efficiency of on-Chip Caches Exploiting Hybrid Memory Structure.
Proceedings of the 28th International Symposium on Power and Timing Modeling, 2018

Worst-Case Performance Analysis Under Random Telegraph Noise Induced Threshold Voltage Variability.
Proceedings of the 28th International Symposium on Power and Timing Modeling, 2018

Low-Power and High-Linearity Inductorless Low-Noise Amplifiers with Active-Shunt-Feedback in 65-nm CMOS Technology.
Proceedings of the IEEE 61st International Midwest Symposium on Circuits and Systems, 2018

Process variation aware D-Flip-Flop design using regression analysis.
Proceedings of the 19th International Symposium on Quality Electronic Design, 2018

Independent N-Well And P-Well Biasing For Minimum Leakage Energy Operation.
Proceedings of the 24th IEEE International Symposium on On-Line Testing And Robust System Design, 2018

An Integrated Optical Parallel Multiplier Exploiting Approximate Binary Logarithms Towards Light Speed Data Processing.
Proceedings of the 2018 IEEE International Conference on Rebooting Computing, 2018

Multi-Level Optimization for Large Fan-In Optical Logic Circuits Using Integrated Nanophotonics.
Proceedings of the 2018 IEEE International Conference on Rebooting Computing, 2018

PVT2: process, voltage, temperature and time-dependent variability in scaled CMOS process.
Proceedings of the International Conference on Computer-Aided Design, 2018

A Low Input Referred Noise and Low Crosstalk Noise 25 Gb/s Transimpedance Amplifier with Inductor-Less Bandwidth Compensation.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2018

2017
A Necessary and Sufficient Condition of Supply and Threshold Voltages in CMOS Circuits for Minimum Energy Point Operation.
IEICE Transactions, 2017

A Minimum Energy Point Tracking Algorithm Based on Dynamic Voltage Scaling and Adaptive Body Biasing.
IEICE Transactions, 2017

On-chip temperature and process variation sensing using a reconfigurable Ring Oscillator.
Proceedings of the 2017 International Symposium on VLSI Design, Automation and Test, 2017

Pin accessibility evaluating model for improving routability of VLSI designs.
Proceedings of the 30th IEEE International System-on-Chip Conference, 2017

Effect of supply voltage on random telegraph noise of transistors under switching condition.
Proceedings of the 27th International Symposium on Power and Timing Modeling, 2017

2016
Analytical Stability Modeling for CMOS Latches in Low Voltage Operation.
IEICE Transactions, 2016

2016 ASP-DAC.
IEEE Design & Test, 2016

Minimum energy point tracking using combined dynamic voltage scaling and adaptive body biasing.
Proceedings of the 29th IEEE International System-on-Chip Conference, 2016

Fully digital on-chip memory using minimum height standard cells for near-threshold voltage computing.
Proceedings of the 26th International Workshop on Power and Timing Modeling, 2016

Variability- and correlation-aware logical effort for near-threshold circuit design.
Proceedings of the 17th International Symposium on Quality Electronic Design, 2016

A highly-dense mixed grained reconfigurable architecture with overlay crossbar interconnect using via-switch.
Proceedings of the 26th International Conference on Field Programmable Logic and Applications, 2016

On-chip monitoring and compensation scheme with fine-grain body biasing for robust and energy-efficient operations.
Proceedings of the 21st Asia and South Pacific Design Automation Conference, 2016

A closed-form stability model for cross-coupled inverters operating in sub-threshold voltage region.
Proceedings of the 21st Asia and South Pacific Design Automation Conference, 2016

2015
A Multi-Rate Burst-Mode CDR Using a GVCO With Symmetric Loops for Instantaneous Phase Locking in 65-nm CMOS.
IEEE Trans. on Circuits and Systems, 2015

Wide-Supply-Range All-Digital Leakage Variation Sensor for On-Chip Process and Temperature Monitoring.
J. Solid-State Circuits, 2015

Layout Generator with Flexible Grid Assignment for Area Efficient Standard Cell.
IPSJ Trans. System LSI Design Methodology, 2015

Statistical Timing Modeling Based on a Lognormal Distribution Model for Near-Threshold Circuit Optimization.
IEICE Transactions, 2015

A Forward/Reverse Body Bias Generator with Wide Supply-Range down to Threshold Voltage.
IEICE Transactions, 2015

Impact of Cell Distance and Well-contact Density on Neutron-induced Multiple Cell Upsets.
IEICE Transactions, 2015

An impact of process variation on supply voltage dependence of logic path delay variation.
Proceedings of the VLSI Design, Automation and Test, 2015

An energy-efficient on-chip memory structure for variability-aware near-threshold operation.
Proceedings of the Sixteenth International Symposium on Quality Electronic Design, 2015

Energy reduction by built-in body biasing with single supply voltage operation.
Proceedings of the Sixteenth International Symposium on Quality Electronic Design, 2015

Session 23 - Modeling emerging devices.
Proceedings of the 2015 IEEE Custom Integrated Circuits Conference, 2015

A 25-Gb/s 480-mW CMOS modulator driver using area-efficient 3D inductor peaking.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2015

Microarchitectural-level statistical timing models for near-threshold circuit design.
Proceedings of the 20th Asia and South Pacific Design Automation Conference, 2015

Reliability-configurable mixed-grained reconfigurable array compatible with high-level synthesis.
Proceedings of the 20th Asia and South Pacific Design Automation Conference, 2015

2014
Frequency-Independent Warning Detection Sequential for Dynamic Voltage and Frequency Scaling in ASICs.
IEEE Trans. VLSI Syst., 2014

On-Chip Measurement of Rise/Fall Gate Delay Using Reconfigurable Ring Oscillator.
IEEE Trans. on Circuits and Systems, 2014

Reliability-Configurable Mixed-Grained Reconfigurable Array Supporting C-Based Design and Its Irradiation Testing.
IEICE Transactions, 2014

Radiation-Hardened PLL with a Switchable Dual Modular Redundancy Structure.
IEICE Transactions, 2014

Analysis of Radiation-Induced Clock-Perturbation in Phase-Locked Loop.
IEICE Transactions, 2014

A Body Bias Generator with Low Supply Voltage for Within-Die Variability Compensation.
IEICE Transactions, 2014

Characterization and compensation of performance variability using on-chip monitors.
Proceedings of the Technical Papers of 2014 International Symposium on VLSI Design, 2014

Design methodology of process variation tolerant D-Flip-Flops for low voltage circuit operation.
Proceedings of the 27th IEEE International System-on-Chip Conference, 2014

Variation-aware Flip-Flop energy optimization for ultra low voltage operation.
Proceedings of the 27th IEEE International System-on-Chip Conference, 2014

Computer simulation of radiation-induced clock-perturbation in phase-locked loop with analog behavioral model.
Proceedings of the Fifteenth International Symposium on Quality Electronic Design, 2014

A 65-nm CMOS burst-mode CDR based on a GVCO with symmetric loops.
Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014

Modeling of advanced devices.
Proceedings of the IEEE 2014 Custom Integrated Circuits Conference, 2014

Impact of random telegraph noise on CMOS logic circuit reliability.
Proceedings of the IEEE 2014 Custom Integrated Circuits Conference, 2014

Variability and Soft-Error Resilience in Dependable VLSI Platform.
Proceedings of the 23rd IEEE Asian Test Symposium, 2014

Wide-supply-range all-digital leakage variation sensor for on-chip process and temperature monitoring.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2014

A body bias generator with wide supply-range down to threshold voltage for within-die variability compensation.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2014

2013
A Radiation-Hard Redundant Flip-Flop to Suppress Multiple Cell Upset by Utilizing the Parasitic Bipolar Effect.
IEICE Transactions, 2013

Standard Cell Structure with Flexible P/N Well Boundaries for Near-Threshold Voltage Operation.
IEICE Transactions, 2013

On-Chip Detection of Process Shift and Process Spread for Post-Silicon Diagnosis and Model-Hardware Correlation.
IEICE Transactions, 2013

Analysis and comparison of XOR cell structures for low voltage circuit design.
Proceedings of the International Symposium on Quality Electronic Design, 2013

Perturbation-immune radiation-hardened PLL with a switchable DMR structure.
Proceedings of the 2013 IEEE 19th International On-Line Testing Symposium (IOLTS), 2013

AMS verification in advanced technologies.
Proceedings of the IEEE 2013 Custom Integrated Circuits Conference, 2013

Dependable VLSI Platform using Robust Fabrics.
Proceedings of the 18th Asia and South Pacific Design Automation Conference, 2013

A 25-Gb/s LD driver with area-effective inductor in a 0.18-µm CMOS.
Proceedings of the 18th Asia and South Pacific Design Automation Conference, 2013

2012
Area-efficient reconfigurable-array-based oscillator for standard cell characterisation.
IET Circuits, Devices & Systems, 2012

Area-Effective Inductive Peaking with Interwoven Inductor for High-Speed Laser-Diode Driver for Optical Communication System.
IEICE Transactions, 2012

A Standard Cell Optimization Method for Near-Threshold Voltage Operations.
Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, 2012

A flexible structure of standard cell and its optimization method for near-threshold voltage operation.
Proceedings of the 30th International IEEE Conference on Computer Design, 2012

Modeling & design for variability and reliability.
Proceedings of the IEEE 2012 Custom Integrated Circuits Conference, 2012

On-Chip Detection of Process Shift and Process Spread for Silicon Debugging and Model-Hardware Correlation.
Proceedings of the 21st IEEE Asian Test Symposium, 2012

A 16Gb/s area-efficient LD driver with interwoven inductor in a 0.18µm CMOS.
Proceedings of the 17th Asia and South Pacific Design Automation Conference, 2012

2011
Variation-Tolerance of a 65-nm Error-Hardened Dual-Modular-Redundancy Flip-Flop Measured by Shift-Register-Based Monitor Structures.
IEICE Transactions, 2011

Modeling of Random Telegraph Noise under circuit operation - Simulation and measurement of RTN-induced delay fluctuation.
Proceedings of the 12th International Symposium on Quality Electronic Design, 2011

Bandwidth enhancement for high speed amplifier utilizing mutually coupled on-chip inductors.
Proceedings of the International SoC Design Conference, 2011

A 10.3Gbps translmpedance amplifier with mutually coupled inductors in 0.18-μm CMOS.
Proceedings of the International SoC Design Conference, 2011

Dependable VLSI Program in Japan: Program Overview and the Current Status of Dependable VLSI Platform Project.
Proceedings of the 20th IEEE Asian Test Symposium, 2011

An area effective forward/reverse body bias generator for within-die variability compensation.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2011

Correlations between well potential and SEUs measured by well-potential perturbation detectors in 65nm.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2011

A 65nm flip-flop array to measure soft error resiliency against high-energy neutron and alpha particles.
Proceedings of the 16th Asia South Pacific Design Automation Conference, 2011

2010
Effect of Regularity-Enhanced Layout on Variability and Circuit Performance of Standard Cells.
IPSJ Trans. System LSI Design Methodology, 2010

Message from the Editor-in-Chief.
IPSJ Trans. System LSI Design Methodology, 2010

An Area/Delay Efficient Dual-Modular Flip-Flop with Higher SEU/SET Immunity.
IEICE Transactions, 2010

Variation-tolerant design of D-flipflops.
Proceedings of the Annual IEEE International SoC Conference, SoCC 2010, 2010

A design procedure of predictive RF MOSFET model for compatibility with ITRS.
Proceedings of the Annual IEEE International SoC Conference, SoCC 2010, 2010

Warning Prediction Sequential for Transient Error Prevention.
Proceedings of the 25th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, 2010

A 16Gbps laser-diode driver with interwoven peaking inductors in 0.18-µm CMOS.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2010

2009
Statistical Gate Delay Model for Multiple Input Switching.
IEICE Transactions, 2009

Erect of regularity-enhanced layout on printability and circuit performance of standard cells.
Proceedings of the 10th International Symposium on Quality of Electronic Design (ISQED 2009), 2009

Modeling of passive elements and reliability.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2009

Dependable VLSI: device, design and architecture: how should they cooperate?
Proceedings of the 14th Asia South Pacific Design Automation Conference, 2009

2008
Accurate Estimation of the Worst-case Delay in Statistical Static Timing Analysis.
IPSJ Trans. System LSI Design Methodology, 2008

Welcome to TSLDM - A New Open-Access Online Journal from IPSJ.
IPSJ Trans. System LSI Design Methodology, 2008

Analytical Model of Static Noise Margin in CMOS SRAM for Variation Consideration.
IEICE Transactions, 2008

Timing Analysis Considering Temporal Supply Voltage Fluctuation.
IEICE Transactions, 2008

Performance optimization by track swapping on critical paths utilizing random variations for FPGAS.
Proceedings of the FPL 2008, 2008

A variation-aware constant-order optimization scheme utilizing delay detectors to search for fastest paths on FPGAS.
Proceedings of the FPL 2008, 2008

Speed and yield enhancement by track swapping on critical paths utilizing random variations for FPGAs.
Proceedings of the ACM/SIGDA 16th International Symposium on Field Programmable Gate Arrays, 2008

Session 2 - Statistical modeling.
Proceedings of the IEEE 2008 Custom Integrated Circuits Conference, 2008

Best ways to use billions of devices on a chip - Error predictive, defect tolerant and error recovery designs.
Proceedings of the 13th Asia South Pacific Design Automation Conference, 2008

Statistical gate delay model for Multiple Input Switching.
Proceedings of the 13th Asia South Pacific Design Automation Conference, 2008

2007
Optimal Termination of On-Chip Transmission-Lines for High-Speed Signaling.
IEICE Transactions, 2007

Manufacturability-Aware Design of Standard Cells.
IEICE Transactions, 2007

Low-Power Design of CML Driver for On-Chip Transmission-Lines Using Impedance-Unmatched Driver.
IEICE Transactions, 2007

A 90 nm 48 x 48 LUT-Based FPGA Enhancing Speed and Yield Utilizing Within-Die Delay Variations.
IEICE Transactions, 2007

A 90 nm LUT Array for Speed and Yield Enhancement by Utilizing Within-Die Delay Variations.
IEICE Transactions, 2007

Timing Analysis Considering Spatial Power/Ground Level Variation.
IEICE Transactions, 2007

Worst-case delay analysis considering the variability of transistors and interconnects.
Proceedings of the 2007 International Symposium on Physical Design, 2007

A 90nm 8×16 FPGA Enhancing Speed and Yield Utilizing Within-Die Variations.
Proceedings of the 12th Conference on Asia South Pacific Design Automation, 2007

A 10Gbps/channel On-Chip Signaling Circuit with an Impedance-Unmatched CML Driver in 90nm CMOS Technology.
Proceedings of the 12th Conference on Asia South Pacific Design Automation, 2007

2006
Alternate Self-Shielding for High-Speed and Reliable On-Chip Global Interconnect.
IEICE Transactions, 2006

Interconnect RL Extraction Based on Transfer Characteristics of Transmission-Line.
IEICE Transactions, 2006

Variability: Modeling and Its Impact on Design.
IEICE Transactions, 2006

Special Section on VLSI Design and CAD Algorithms.
IEICE Transactions, 2006

A Leakage Reduction Scheme for Sleep Transistors with Decoupling Capacitors in the Deep Submicron Era.
IEICE Transactions, 2006

Si-Substrate Modeling toward Substrate-Aware Interconnect Resistance and Inductance Extraction in SoC Design.
IEICE Transactions, 2006

A Detailed Vth-Variation Analysis for Sub-100-nm Embedded SRAM Design.
Proceedings of the 2006 IEEE International SOC Conference, Austin, Texas, USA, 2006

Consideration of Transition-Time Variability in Statistical Timing Analysis.
Proceedings of the 2006 IEEE International SOC Conference, Austin, Texas, USA, 2006

A Yield and Speed Enhancement Technique Using Reconfigurable Devices Against Within-Die Variations on the Nanometer Regime.
Proceedings of the 2006 International Conference on Field Programmable Logic and Applications (FPL), 2006

Interconnect RL extraction at a single representative frequency.
Proceedings of the 2006 Conference on Asia South Pacific Design Automation: ASP-DAC 2006, 2006

Measurement results of within-die variations on a 90nm LUT array for speed and yield enhancement of reconfigurable devices.
Proceedings of the 2006 Conference on Asia South Pacific Design Automation: ASP-DAC 2006, 2006

2005
Performance Limitation of On-Chip Global Interconnects for High-Speed Signaling.
IEICE Transactions, 2005

Successive Pad Assignment for Minimizing Supply Voltage Drop.
IEICE Transactions, 2005

Effects of On-Chip Inductance on Power Distribution Grid.
IEICE Transactions, 2005

A Performance Prediction of Clock Generation PLLs: A Ring Oscillator Based PLL and an LC Oscillator Based PLL.
IEICE Transactions, 2005

A Resource-Shared VLIW Processor for Low-Power On-Chip Multiprocessing in the Nanometer Era.
IEICE Transactions, 2005

Statistical Analysis of Clock Skew Variation in H-Tree Structure.
IEICE Transactions, 2005

Statistical Analysis of Clock Skew Variation in H-Tree Structure.
Proceedings of the 6th International Symposium on Quality of Electronic Design (ISQED 2005), 2005

Effects of on-chip inductance on power distribution grid.
Proceedings of the 2005 International Symposium on Physical Design, 2005

Design guideline for resistive termination of on-chip high-speed interconnects.
Proceedings of the IEEE 2005 Custom Integrated Circuits Conference, 2005

Substrate and phase noise characterization.
Proceedings of the IEEE 2005 Custom Integrated Circuits Conference, 2005

A yield and speed enhancement scheme under within-die variations on 90nm LUT array.
Proceedings of the IEEE 2005 Custom Integrated Circuits Conference, 2005

Return path selection for loop RL extraction.
Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005

Design and measurement of 6.4 Gbps 8: 1 multiplexer in 0.18µm CMOS process.
Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005

Successive pad assignment algorithm to optimize number and location of power supply pad using incremental matrix inversion.
Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005

A resource-shared VLIW processor architecture for area-efficient on-chip multiprocessing.
Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005

Timing analysis considering temporal supply voltage fluctuation.
Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005

2004
Equivalent waveform propagation for static timing analysis.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2004

A Comprehensive Simulation and Test Environment for Prototype VLSI Verification.
IEICE Transactions, 2004

Automatic Generation of Standard Cell Library in VDSM Technologies.
Proceedings of the 5th International Symposium on Quality of Electronic Design (ISQED 2004), 2004

RTL/ISS co-modeling methodology for embedded processor using SystemC.
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004

Modelling and optimization of on-chip spiral inductor in S-parameter domain.
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004

Timing analysis considering spatial power/ground level variation.
Proceedings of the 2004 International Conference on Computer-Aided Design, 2004

Performance limitation of on-chip global interconnects for high-speed signaling.
Proceedings of the IEEE 2004 Custom Integrated Circuits Conference, 2004

An SoC architecture and its design methodology using unifunctional heterogeneous processor array.
Proceedings of the 2004 Conference on Asia South Pacific Design Automation: Electronic Design and Solution Fair 2004, 2004

Representative frequency for interconnect R(f)L(f)C extraction.
Proceedings of the 2004 Conference on Asia South Pacific Design Automation: Electronic Design and Solution Fair 2004, 2004

A performance comparison of PLLs for clock generation using ring oscillator VCO and LC oscillator in a digital CMOS process.
Proceedings of the 2004 Conference on Asia South Pacific Design Automation: Electronic Design and Solution Fair 2004, 2004

2003
Capturing crosstalk-induced waveform for accurate static timing analysis.
Proceedings of the 2003 International Symposium on Physical Design, 2003

Statistical modeling of gate-delay variation with consideration of intra-gate variability.
Proceedings of the 2003 International Symposium on Circuits and Systems, 2003

A Statistical Gate-Delay Model Considering Intra-Gate Variability.
Proceedings of the 2003 International Conference on Computer-Aided Design, 2003

Equivalent Waveform Propagation for Static Timing Analysis.
Proceedings of the 2003 International Conference on Computer-Aided Design, 2003

A statistical gate delay model for intra-chip and inter-chip variabilities.
Proceedings of the 2003 Asia and South Pacific Design Automation Conference, 2003

Standard cell libraries with various driving strength cells for 0.13, 0.18 and 0.35 μm technologies.
Proceedings of the 2003 Asia and South Pacific Design Automation Conference, 2003

2002
Experimental Study on Cell-Base High-Performance Datapath Design.
Proceedings of the 11th IEEE/ACM International Workshop on Logic & Synthesis, 2002

Crosstalk noise optimization by post-layout transistor sizing.
Proceedings of 2002 International Symposium on Physical Design, 2002

2001
ST: PERL package for simulation and test environment.
Proceedings of the 2001 International Symposium on Circuits and Systems, 2001

Crosstalk Noise Estimation for Generic RC Trees.
Proceedings of the 19th International Conference on Computer Design (ICCD 2001), 2001

A dynamically phase adjusting PLL with a variable delay.
Proceedings of ASP-DAC 2001, 2001

Beyond the red brick wall (panel): challenges and solutions in 50nm physical design.
Proceedings of ASP-DAC 2001, 2001

A vector-pipeline DSP for low-rate videophones.
Proceedings of ASP-DAC 2001, 2001

Post-layout transistor sizing for power reduction in cell-based design.
Proceedings of ASP-DAC 2001, 2001

2000
A performance optimization method by gate sizing using statistical static timing analysis.
Proceedings of the 2000 International Symposium on Physical Design, 2000

Statistical modeling of device characteristics with systematic fluctuation.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2000

Statistical delay calculation with vector synthesis model.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2000

A method for linking process-level variability to system performances.
Proceedings of ASP-DAC 2000, 2000

1999
A Practical Gate Resizing Technique Considering Glitch Reduction for Low Power Design.
Proceedings of the 36th Conference on Design Automation, 1999

1998
Model-adaptable MOSFET parameter-extraction method using an intermediate model.
IEEE Trans. on CAD of Integrated Circuits and Systems, 1998

A power optimization method considering glitch reduction by gate sizing.
Proceedings of the 1998 International Symposium on Low Power Electronics and Design, 1998

Proposal of a timing model for CMOS logic gates driving a CRC load.
Proceedings of the 1998 IEEE/ACM International Conference on Computer-Aided Design, 1998

1997
A current mode cyclic A/D converter with a 0.8 μm CMOS process.
Proceedings of the ASP-DAC '97 Asia and South Pacific Design Automation Conference, 1997

A functional memory type parallel processor for vector quantization.
Proceedings of the ASP-DAC '97 Asia and South Pacific Design Automation Conference, 1997

1996
Timing and Power Optimization by Gate Sizing Considering False Paths.
Proceedings of the 6th Great Lakes Symposium on VLSI (GLS-VLSI '96), 1996

1995
An iterative gate sizing approach with accurate delay evaluation.
Proceedings of the 1995 IEEE/ACM International Conference on Computer-Aided Design, 1995

A model-adaptable MOSFET parameter extraction system.
Proceedings of the 1995 Conference on Asia Pacific Design Automation, Makuhari, Massa, Chiba, Japan, August 29, 1995

1993
Layout-driven module selection for register-transfer synthesis of sub-micron ASIC's.
Proceedings of the 1993 IEEE/ACM International Conference on Computer-Aided Design, 1993

1991
Branch-and-Bound Placement for Building Block Layout.
Proceedings of the 28th Design Automation Conference, 1991

1989
An efficient algorithm for layout compaction problem with symmetry constraints.
Proceedings of the 1989 IEEE International Conference on Computer-Aided Design, 1989

1987
System design of a special-purpose computer for LSI design rule checking.
Systems and Computers in Japan, 1987


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