Hidetoshi Onodera
Orcid: 0000-0001-5198-0668
According to our database1,
Hidetoshi Onodera
authored at least 206 papers
between 1987 and 2023.
Collaborative distances:
Collaborative distances:
Awards
IEEE Fellow
IEEE Fellow 2018, "For contributions to variation-aware design and analysis of integrated circuits".
Timeline
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On csauthors.net:
Bibliography
2023
Approximation-Based System Implementation for Real-Time Minimum Energy Point Tracking over a Wide Operating Performance Region.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., March, 2023
2022
NCTUcell: A DDA- and Delay-Aware Cell Library Generator for FinFET Structure With Implicitly Adjustable Grid Map.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022
Zero-Aware Fine-Grained Power Gating for Standard-Cell Memories in Voltage-Scaled Circuits.
Proceedings of the 35th IEEE International System-on-Chip Conference, 2022
Approximation-Based Implementation for a Minimum Energy Point Tracking Algorithm over a Wide Operating Performance Region.
Proceedings of the 13th IEEE Latin America Symposium on Circuits and System, 2022
2021
MOSDA: On-Chip Memory Optimized Sparse Deep Neural Network Accelerator With Efficient Index Matching.
IEEE Open J. Circuits Syst., 2021
IPSJ Trans. Syst. LSI Des. Methodol., 2021
A DLL-Based Body Bias Generator with Independent P-Well and N-Well Biasing for Minimum Energy Operation.
IEICE Trans. Electron., 2021
Evaluation Metrics for the Cost of Data Movement in Deep Neural Network Acceleration.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2021
Supply and Threshold Voltage Scaling for Minimum Energy Operation over a Wide Operating Performance Region.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2021
A Synthesis Method Based on Multi-Stage Optimization for Power-Efficient Integrated Optical Logic Circuits.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2021
CDF Distance Based Statistical Parameter Extraction Using Nonlinear Delay Variation Models.
Proceedings of the 27th IEEE International Symposium on On-Line Testing and Robust System Design, 2021
Proceedings of the 58th ACM/IEEE Design Automation Conference, 2021
2020
Design of a 45 Gb/s, 98 fJ/bit, 0.02 mm<sup>2</sup> Transimpedance Amplifier with Peaking-Dedicated Inductor in 65-nm CMOS.
IEICE Trans. Electron., 2020
Dynamic Supply and Threshold Voltage Scaling towards Runtime Energy Optimization over a Wide Operating Performance Region.
Proceedings of the 33rd IEEE International System-on-Chip Conference, 2020
A Synthesis Method for Power-Efficient Integrated Optical Logic Circuits Towards Light Speed Processing.
Proceedings of the 2020 IEEE Computer Society Annual Symposium on VLSI, 2020
33.3 Via-Switch FPGA: 65nm CMOS Implementation and Architecture Extension for Al Applications.
Proceedings of the 2020 IEEE International Solid- State Circuits Conference, 2020
Proceedings of the International Conference on Rebooting Computing, 2020
MCell: Multi-Row Cell Layout Synthesis with Resource Constrained MAX-SAT Based Detailed Routing.
Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2020
Proceedings of the GLSVLSI '20: Great Lakes Symposium on VLSI 2020, 2020
A DLL-based Body Bias Generator for Minimum Energy Operation with Independent P-well and N-well Bias.
Proceedings of the 2020 IEEE Asia Pacific Conference on Circuits and Systems, 2020
2019
IPSJ Trans. Syst. LSI Des. Methodol., 2019
Area-efficient fully digital memory using minimum height standard cells for near-threshold voltage computing.
Integr., 2019
On-Chip Cache Architecture Exploiting Hybrid Memory Structures for Near-Threshold Computing.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2019
Impact of On-Chip Inductor and Power-Delivery-Network Stacking on Signal and Power Integrity.
IEICE Trans. Electron., 2019
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2019
IEICE Trans. Electron., 2019
A 45 Gb/s, 98 fJ/bit, 0.02 mm<sup>2</sup> Transimpedance Amplifier with Peaking-Dedicated Inductor in 65-nm CMOS.
Proceedings of the 32nd IEEE International System-on-Chip Conference, 2019
Analysis of Random Telegraph Noise (RTN) at Near-Threshold Operation by Measuring 154k Ring Oscillators.
Proceedings of the IEEE International Reliability Physics Symposium, 2019
NCTUcell: A DDA-Aware Cell Library Generator for FinFET Structure with Implicitly Adjustable Grid Map.
Proceedings of the 56th Annual Design Automation Conference 2019, 2019
BDD-based synthesis of optical logic circuits exploiting wavelength division multiplexing.
Proceedings of the 24th Asia and South Pacific Design Automation Conference, 2019
2018
Via-Switch FPGA: Highly Dense Mixed-Grained Reconfigurable Architecture With Overlay Via-Switch Crossbars.
IEEE Trans. Very Large Scale Integr. Syst., 2018
J. Low Power Electron., 2018
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2018
IEEE Embed. Syst. Lett., 2018
Performance Modeling of VIA-Switch FPGA for Device-Circuit-Architecture Co-Optimization.
Proceedings of the 31st IEEE International System-on-Chip Conference, 2018
Proceedings of the 28th International Symposium on Power and Timing Modeling, 2018
Worst-Case Performance Analysis Under Random Telegraph Noise Induced Threshold Voltage Variability.
Proceedings of the 28th International Symposium on Power and Timing Modeling, 2018
Low-Power and High-Linearity Inductorless Low-Noise Amplifiers with Active-Shunt-Feedback in 65-nm CMOS Technology.
Proceedings of the IEEE 61st International Midwest Symposium on Circuits and Systems, 2018
Proceedings of the 19th International Symposium on Quality Electronic Design, 2018
Proceedings of the 24th IEEE International Symposium on On-Line Testing And Robust System Design, 2018
An Integrated Optical Parallel Multiplier Exploiting Approximate Binary Logarithms Towards Light Speed Data Processing.
Proceedings of the 2018 IEEE International Conference on Rebooting Computing, 2018
Multi-Level Optimization for Large Fan-In Optical Logic Circuits Using Integrated Nanophotonics.
Proceedings of the 2018 IEEE International Conference on Rebooting Computing, 2018
PVT<sup>2</sup>: process, voltage, temperature and time-dependent variability in scaled CMOS process.
Proceedings of the International Conference on Computer-Aided Design, 2018
A Low Input Referred Noise and Low Crosstalk Noise 25 Gb/s Transimpedance Amplifier with Inductor-Less Bandwidth Compensation.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2018
2017
A Necessary and Sufficient Condition of Supply and Threshold Voltages in CMOS Circuits for Minimum Energy Point Operation.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2017
A Minimum Energy Point Tracking Algorithm Based on Dynamic Voltage Scaling and Adaptive Body Biasing.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2017
On-chip temperature and process variation sensing using a reconfigurable Ring Oscillator.
Proceedings of the 2017 International Symposium on VLSI Design, Automation and Test, 2017
Proceedings of the 30th IEEE International System-on-Chip Conference, 2017
Effect of supply voltage on random telegraph noise of transistors under switching condition.
Proceedings of the 27th International Symposium on Power and Timing Modeling, 2017
Power-bandwidth trade-off analysis of multi-stage inverter-type transimpedance amplifier for optical communication.
Proceedings of the IEEE 60th International Midwest Symposium on Circuits and Systems, 2017
2016
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2016
Minimum energy point tracking using combined dynamic voltage scaling and adaptive body biasing.
Proceedings of the 29th IEEE International System-on-Chip Conference, 2016
Fully digital on-chip memory using minimum height standard cells for near-threshold voltage computing.
Proceedings of the 26th International Workshop on Power and Timing Modeling, 2016
Proceedings of the 17th International Symposium on Quality Electronic Design, 2016
A highly-dense mixed grained reconfigurable architecture with overlay crossbar interconnect using via-switch.
Proceedings of the 26th International Conference on Field Programmable Logic and Applications, 2016
On-chip monitoring and compensation scheme with fine-grain body biasing for robust and energy-efficient operations.
Proceedings of the 21st Asia and South Pacific Design Automation Conference, 2016
A closed-form stability model for cross-coupled inverters operating in sub-threshold voltage region.
Proceedings of the 21st Asia and South Pacific Design Automation Conference, 2016
2015
A Multi-Rate Burst-Mode CDR Using a GVCO With Symmetric Loops for Instantaneous Phase Locking in 65-nm CMOS.
IEEE Trans. Circuits Syst. I Regul. Pap., 2015
Wide-Supply-Range All-Digital Leakage Variation Sensor for On-Chip Process and Temperature Monitoring.
IEEE J. Solid State Circuits, 2015
IPSJ Trans. Syst. LSI Des. Methodol., 2015
Statistical Timing Modeling Based on a Lognormal Distribution Model for Near-Threshold Circuit Optimization.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2015
A Forward/Reverse Body Bias Generator with Wide Supply-Range down to Threshold Voltage.
IEICE Trans. Electron., 2015
Impact of Cell Distance and Well-contact Density on Neutron-induced Multiple Cell Upsets.
IEICE Trans. Electron., 2015
An impact of process variation on supply voltage dependence of logic path delay variation.
Proceedings of the VLSI Design, Automation and Test, 2015
An energy-efficient on-chip memory structure for variability-aware near-threshold operation.
Proceedings of the Sixteenth International Symposium on Quality Electronic Design, 2015
Proceedings of the Sixteenth International Symposium on Quality Electronic Design, 2015
Proceedings of the 2015 IEEE Custom Integrated Circuits Conference, 2015
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2015
Microarchitectural-level statistical timing models for near-threshold circuit design.
Proceedings of the 20th Asia and South Pacific Design Automation Conference, 2015
Reliability-configurable mixed-grained reconfigurable array compatible with high-level synthesis.
Proceedings of the 20th Asia and South Pacific Design Automation Conference, 2015
2014
Frequency-Independent Warning Detection Sequential for Dynamic Voltage and Frequency Scaling in ASICs.
IEEE Trans. Very Large Scale Integr. Syst., 2014
IEEE Trans. Circuits Syst. II Express Briefs, 2014
Reliability-Configurable Mixed-Grained Reconfigurable Array Supporting C-Based Design and Its Irradiation Testing.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2014
IEICE Trans. Electron., 2014
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2014
A Body Bias Generator with Low Supply Voltage for Within-Die Variability Compensation.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2014
Proceedings of the Technical Papers of 2014 International Symposium on VLSI Design, 2014
Design methodology of process variation tolerant D-Flip-Flops for low voltage circuit operation.
Proceedings of the 27th IEEE International System-on-Chip Conference, 2014
Proceedings of the 27th IEEE International System-on-Chip Conference, 2014
Computer simulation of radiation-induced clock-perturbation in phase-locked loop with analog behavioral model.
Proceedings of the Fifteenth International Symposium on Quality Electronic Design, 2014
Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014
Proceedings of the IEEE 2014 Custom Integrated Circuits Conference, 2014
Proceedings of the IEEE 2014 Custom Integrated Circuits Conference, 2014
Proceedings of the 23rd IEEE Asian Test Symposium, 2014
A body bias generator with wide supply-range down to threshold voltage for within-die variability compensation.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2014
2013
A Radiation-Hard Redundant Flip-Flop to Suppress Multiple Cell Upset by Utilizing the Parasitic Bipolar Effect.
IEICE Trans. Electron., 2013
Standard Cell Structure with Flexible P/N Well Boundaries for Near-Threshold Voltage Operation.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2013
On-Chip Detection of Process Shift and Process Spread for Post-Silicon Diagnosis and Model-Hardware Correlation.
IEICE Trans. Inf. Syst., 2013
Proceedings of the International Symposium on Quality Electronic Design, 2013
Proceedings of the 2013 IEEE 19th International On-Line Testing Symposium (IOLTS), 2013
Proceedings of the IEEE 2013 Custom Integrated Circuits Conference, 2013
Proceedings of the 18th Asia and South Pacific Design Automation Conference, 2013
Proceedings of the 18th Asia and South Pacific Design Automation Conference, 2013
2012
Area-efficient reconfigurable-array-based oscillator for standard cell characterisation.
IET Circuits Devices Syst., 2012
Area-Effective Inductive Peaking with Interwoven Inductor for High-Speed Laser-Diode Driver for Optical Communication System.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2012
Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, 2012
A flexible structure of standard cell and its optimization method for near-threshold voltage operation.
Proceedings of the 30th International IEEE Conference on Computer Design, 2012
Proceedings of the IEEE 2012 Custom Integrated Circuits Conference, 2012
On-Chip Detection of Process Shift and Process Spread for Silicon Debugging and Model-Hardware Correlation.
Proceedings of the 21st IEEE Asian Test Symposium, 2012
Proceedings of the 17th Asia and South Pacific Design Automation Conference, 2012
2011
Variation-Tolerance of a 65-nm Error-Hardened Dual-Modular-Redundancy Flip-Flop Measured by Shift-Register-Based Monitor Structures.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2011
Modeling of Random Telegraph Noise under circuit operation - Simulation and measurement of RTN-induced delay fluctuation.
Proceedings of the 12th International Symposium on Quality Electronic Design, 2011
Bandwidth enhancement for high speed amplifier utilizing mutually coupled on-chip inductors.
Proceedings of the International SoC Design Conference, 2011
Proceedings of the International SoC Design Conference, 2011
Dependable VLSI Program in Japan: Program Overview and the Current Status of Dependable VLSI Platform Project.
Proceedings of the 20th IEEE Asian Test Symposium, 2011
An area effective forward/reverse body bias generator for within-die variability compensation.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2011
Correlations between well potential and SEUs measured by well-potential perturbation detectors in 65nm.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2011
A 65nm flip-flop array to measure soft error resiliency against high-energy neutron and alpha particles.
Proceedings of the 16th Asia South Pacific Design Automation Conference, 2011
2010
Effect of Regularity-Enhanced Layout on Variability and Circuit Performance of Standard Cells.
IPSJ Trans. Syst. LSI Des. Methodol., 2010
IEICE Trans. Electron., 2010
Proceedings of the Annual IEEE International SoC Conference, SoCC 2010, 2010
Proceedings of the Annual IEEE International SoC Conference, SoCC 2010, 2010
Proceedings of the 25th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, 2010
Proceedings of the IEEE Custom Integrated Circuits Conference, 2010
2009
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2009
Erect of regularity-enhanced layout on printability and circuit performance of standard cells.
Proceedings of the 10th International Symposium on Quality of Electronic Design (ISQED 2009), 2009
Proceedings of the IEEE Custom Integrated Circuits Conference, 2009
Proceedings of the 14th Asia South Pacific Design Automation Conference, 2009
2008
IPSJ Trans. Syst. LSI Des. Methodol., 2008
IPSJ Trans. Syst. LSI Des. Methodol., 2008
IEICE Trans. Electron., 2008
IEICE Trans. Inf. Syst., 2008
Performance optimization by track swapping on critical paths utilizing random variations for FPGAS.
Proceedings of the FPL 2008, 2008
A variation-aware constant-order optimization scheme utilizing delay detectors to search for fastest paths on FPGAS.
Proceedings of the FPL 2008, 2008
Speed and yield enhancement by track swapping on critical paths utilizing random variations for FPGAs.
Proceedings of the ACM/SIGDA 16th International Symposium on Field Programmable Gate Arrays, 2008
Proceedings of the IEEE 2008 Custom Integrated Circuits Conference, 2008
Best ways to use billions of devices on a chip - Error predictive, defect tolerant and error recovery designs.
Proceedings of the 13th Asia South Pacific Design Automation Conference, 2008
2007
IEICE Trans. Electron., 2007
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2007
Low-Power Design of CML Driver for On-Chip Transmission-Lines Using Impedance-Unmatched Driver.
IEICE Trans. Electron., 2007
A 90 nm 48 x 48 LUT-Based FPGA Enhancing Speed and Yield Utilizing Within-Die Delay Variations.
IEICE Trans. Electron., 2007
A 90 nm LUT Array for Speed and Yield Enhancement by Utilizing Within-Die Delay Variations.
IEICE Trans. Electron., 2007
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2007
Worst-case delay analysis considering the variability of transistors and interconnects.
Proceedings of the 2007 International Symposium on Physical Design, 2007
Proceedings of the 12th Conference on Asia South Pacific Design Automation, 2007
A 10Gbps/channel On-Chip Signaling Circuit with an Impedance-Unmatched CML Driver in 90nm CMOS Technology.
Proceedings of the 12th Conference on Asia South Pacific Design Automation, 2007
2006
IEICE Trans. Electron., 2006
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2006
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2006
A Leakage Reduction Scheme for Sleep Transistors with Decoupling Capacitors in the Deep Submicron Era.
IEICE Trans. Electron., 2006
Si-Substrate Modeling toward Substrate-Aware Interconnect Resistance and Inductance Extraction in SoC Design.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2006
Proceedings of the 2006 IEEE International SOC Conference, Austin, Texas, USA, 2006
Proceedings of the 2006 IEEE International SOC Conference, Austin, Texas, USA, 2006
A Yield and Speed Enhancement Technique Using Reconfigurable Devices Against Within-Die Variations on the Nanometer Regime.
Proceedings of the 2006 International Conference on Field Programmable Logic and Applications (FPL), 2006
Proceedings of the 2006 Conference on Asia South Pacific Design Automation: ASP-DAC 2006, 2006
Measurement results of within-die variations on a 90nm LUT array for speed and yield enhancement of reconfigurable devices.
Proceedings of the 2006 Conference on Asia South Pacific Design Automation: ASP-DAC 2006, 2006
2005
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2005
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2005
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2005
A Performance Prediction of Clock Generation PLLs: A Ring Oscillator Based PLL and an LC Oscillator Based PLL.
IEICE Trans. Electron., 2005
A Resource-Shared VLIW Processor for Low-Power On-Chip Multiprocessing in the Nanometer Era.
IEICE Trans. Electron., 2005
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2005
Proceedings of the IEEE 2005 Custom Integrated Circuits Conference, 2005
Proceedings of the IEEE 2005 Custom Integrated Circuits Conference, 2005
Proceedings of the IEEE 2005 Custom Integrated Circuits Conference, 2005
Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005
Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005
Successive pad assignment algorithm to optimize number and location of power supply pad using incremental matrix inversion.
Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005
A resource-shared VLIW processor architecture for area-efficient on-chip multiprocessing.
Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005
2004
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2004
IEICE Trans. Inf. Syst., 2004
Proceedings of the 5th International Symposium on Quality of Electronic Design (ISQED 2004), 2004
RTL/ISS co-modeling methodology for embedded processor using SystemC.
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004
Modelling and optimization of on-chip spiral inductor in S-parameter domain.
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004
Proceedings of the IEEE 2004 Custom Integrated Circuits Conference, 2004
An SoC architecture and its design methodology using unifunctional heterogeneous processor array.
Proceedings of the 2004 Conference on Asia South Pacific Design Automation: Electronic Design and Solution Fair 2004, 2004
A performance comparison of PLLs for clock generation using ring oscillator VCO and LC oscillator in a digital CMOS process.
Proceedings of the 2004 Conference on Asia South Pacific Design Automation: Electronic Design and Solution Fair 2004, 2004
2003
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2003
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2003
Realistic Delay Calculation Based on Measured Intra-Chip and Inter-Chip Variabilities with the Size Dependence.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2003
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2003
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2003
Proceedings of the 2003 International Symposium on Physical Design, 2003
Statistical modeling of gate-delay variation with consideration of intra-gate variability.
Proceedings of the 2003 International Symposium on Circuits and Systems, 2003
Proceedings of the 2003 International Conference on Computer-Aided Design, 2003
Proceedings of the 2003 Asia and South Pacific Design Automation Conference, 2003
Standard cell libraries with various driving strength cells for 0.13, 0.18 and 0.35 μm technologies.
Proceedings of the 2003 Asia and South Pacific Design Automation Conference, 2003
2002
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2002
Experimental Study on Cell-Base High-Performance Datapath Design.
Proceedings of the 11th IEEE/ACM International Workshop on Logic & Synthesis, 2002
Proceedings of 2002 International Symposium on Physical Design, 2002
Proceedings of the IEEE 2002 Custom Integrated Circuits Conference, 2002
2001
Proceedings of the 2001 International Symposium on Circuits and Systems, 2001
Proceedings of ASP-DAC 2001, 2001
Proceedings of ASP-DAC 2001, 2001
Proceedings of ASP-DAC 2001, 2001
2000
A performance optimization method by gate sizing using statistical static timing analysis.
Proceedings of the 2000 International Symposium on Physical Design, 2000
Proceedings of the IEEE International Symposium on Circuits and Systems, 2000
Proceedings of the IEEE International Symposium on Circuits and Systems, 2000
Proceedings of ASP-DAC 2000, 2000
1999
A Practical Gate Resizing Technique Considering Glitch Reduction for Low Power Design.
Proceedings of the 36th Conference on Design Automation, 1999
1998
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1998
Proceedings of the 1998 International Symposium on Low Power Electronics and Design, 1998
Proceedings of the 1998 IEEE/ACM International Conference on Computer-Aided Design, 1998
1997
Proceedings of the ASP-DAC '97 Asia and South Pacific Design Automation Conference, 1997
Proceedings of the ASP-DAC '97 Asia and South Pacific Design Automation Conference, 1997
1996
Proceedings of the 6th Great Lakes Symposium on VLSI (GLS-VLSI '96), 1996
1995
Proceedings of the 1995 IEEE/ACM International Conference on Computer-Aided Design, 1995
Proceedings of the 1995 Conference on Asia Pacific Design Automation, Makuhari, Massa, Chiba, Japan, August 29, 1995
1993
Proceedings of the 1993 IEEE/ACM International Conference on Computer-Aided Design, 1993
1991
Proceedings of the 28th Design Automation Conference, 1991
1989
Proceedings of the 1989 IEEE International Conference on Computer-Aided Design, 1989
1987
Syst. Comput. Jpn., 1987