Kazutoshi Kobayashi

Orcid: 0000-0002-7139-7274

According to our database1, Kazutoshi Kobayashi authored at least 87 papers between 1997 and 2024.

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Bibliography

2024
Soft-Error Tolerance by Guard-Gate Structures on Flip-Flops in 22 and 65 nm FD-SOI Technologies.
IEICE Trans. Electron., 2024

Measuring SET Pulse Widths in pMOSFETs and nMOSFETs Separately by Heavy Ion and Neutron Irradiation.
IEICE Trans. Electron., 2024

An Approach to Neutron-Induced SER Evaluation Using a Clinical 290 MeV/ u Carbon Beam and Particle Transport Simulations.
Proceedings of the IEEE International Reliability Physics Symposium, 2024

A Partially-redundant Flip-flip Suitable for Mitigating Single Event Upsets in a FD-SOI Process with Low Performance Overhead.
Proceedings of the IEEE International Reliability Physics Symposium, 2024

2023
Nonvolatile Storage Cells Using FiCC for IoT Processors with Intermittent Operations.
IEICE Trans. Electron., October, 2023

Disturbance Aware Dynamic Power Reduction in Synchronous 2RW Dual-Port 8T SRAM by Self-Adjusting Wordline Pulse Timing.
IEEE J. Solid State Circuits, 2023

Radiation Hardened Flip-Flops with low Area, Delay and Power Overheads in a 65 nm bulk process.
Proceedings of the IEEE International Reliability Physics Symposium, 2023

Ultra Long-term Measurement Results of BTI-induced Aging Degradation on 7-nm Ring Oscillators.
Proceedings of the IEEE International Reliability Physics Symposium, 2023

A 13-bit Radiation-Hardened SAR-ADC with Error Correction by Adaptive Topology Transformation.
Proceedings of the IEEE International Reliability Physics Symposium, 2023

Radiation Hardness Evaluations of a Stacked Flip Flop in a 22 nm FD-SOI Process by Heavy-Ion Irradiation.
Proceedings of the 29th International Symposium on On-Line Testing and Robust System Design, 2023

SEU Sensitivity of PMOS and NMOS Transistors in a 65 nm Bulk Process by α-Particle Irradiation.
Proceedings of the International Conference on IC Design and Technology, 2023

Frequency Dependency of Soft Error Rates Based on Dynamic Soft Error Measurements.
Proceedings of the International Conference on IC Design and Technology, 2023

Scalable Highly Integrated Quantum Bit Error Correction System by Classical Electronics.
Proceedings of the 15th IEEE International Conference on ASIC, 2023

Ring Oscillators with identical Circuit Structure to Measure Bias Temperature Instability.
Proceedings of the 15th IEEE International Conference on ASIC, 2023

2022
Nonvolatile Flip-Flops Using FiCC for IoT Processors with Intermittent Operations.
Proceedings of the 65th IEEE International Midwest Symposium on Circuits and Systems, 2022

An Aging Degradation Suppression Scheme at Constant Performance by Controlling Supply Voltage and Body Bias in a 65 nm Fully-Depleted Silicon-On-Insulator Process.
Proceedings of the IEEE International Reliability Physics Symposium, 2022

Radiation Hardened Flip-Flops Minimizing Area, Power, and Delay Overheads with 1/100 Lower α-SER in a 130 nm Bulk Process.
Proceedings of the 28th IEEE International Symposium on On-Line Testing and Robust System Design, 2022

Zero-standby-power Nonvolatile Standard Cell Memory Using FiCC for IoT Processors with Intermittent Operations.
Proceedings of the IEEE Symposium in Low-Power and High-Speed Chips, 2022

2021
Cost-Effective Test Screening Method on 40-nm Embedded SRAMs for Low-Power MCUs.
IEEE Trans. Very Large Scale Integr. Syst., 2021

An Analysis of Local BTI Variation with Ring-Oscillator in Advanced Processes and Its Impact on Logic Circuit and SRAM.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2021

An E-mode p-GaN HEMT monolithically-integrated three-level gate driver operating with a single voltage supply.
IEICE Electron. Express, 2021

A Bit-Error Rate Measurement and Error Analysis of Wireline Data Transmission using Current Source Model for Single Event Effect under Irradiation Environment.
J. Electron. Test., 2021

Bias Temperature Instability Depending on Body Bias through Buried Oxide (BOX) Layer in a 65 nm Fully-Depleted Silicon-On-Insulator Process.
Proceedings of the IEEE International Reliability Physics Symposium, 2021

Nonvolatile SRAM Using Fishbone-in-Cage Capacitor in a 180 nm Standard CMOS Process for Zero-Standby and Instant-Powerup Embedded Memory on IoT.
Proceedings of the IEEE Symposium in Low-Power and High-Speed Chips, 2021

2020
An Efficient and Accurate Time Step Control Method for Power Device Transient Simulation Utilizing Dominant Time Constant Approximation.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020

Universal NBTI Compact Model Replicating AC Stress/Recovery from a Single-shot Long-term DC Measurement.
IPSJ Trans. Syst. LSI Des. Methodol., 2020

Evaluation of Heavy-Ion-Induced Single Event Upset Cross Sections of a 65-nm Thin BOX FD-SOI Flip-Flops Composed of Stacked Inverters.
IEICE Trans. Electron., 2020

2019
Characterizing SRAM and FF soft error rates with measurement and simulation.
Integr., 2019

Monolithic integration of gate driver and p-GaN power HEMT for MHz-switching implemented by e-mode GaN-on-SOI process.
IEICE Electron. Express, 2019

An Accurate Device-Level Simulation Method to Estimate Cross Sections of Single Event Upsets by Silicon Thickness in Raised Layer.
Proceedings of the IEEE International Reliability Physics Symposium, 2019

Impact of Combinational Logic Delay for Single Event Upset on Flip Flops in a 65 nm FDSOI Process.
Proceedings of the IEEE International Reliability Physics Symposium, 2019

Total Ionizing Dose Effects by alpha irradiation on circuit performance and SEU tolerance in thin BOX FDSOI process.
Proceedings of the 25th IEEE International Symposium on On-Line Testing and Robust System Design, 2019

Compact Modeling of NBTI Replicating AC Stress / Recovery from a Single-shot Long-term DC Measurement.
Proceedings of the 25th IEEE International Symposium on On-Line Testing and Robust System Design, 2019

Comparison of Radiation Hardness of Stacked Transmission-Gate Flip Flop and Stacked Tristate-Inverter Flip Flop in a 65 nm Thin BOX FDSOI Process.
Proceedings of the 25th IEEE International Symposium on On-Line Testing and Robust System Design, 2019

Monolithically integrated GaN power ICs designed using the MIT virtual source GaNFET (MVSG) compact model for enhancement-mode p-GaN gate power HEMTs, logic transistors and resistors.
Proceedings of the 49th European Solid-State Device Research Conference, 2019

Soft-Error Tolerance Depending on Supply Voltage by Heavy Ions on Radiation-Hardened Flip Flops in a 65 nm Bulk Process.
Proceedings of the 13th IEEE International Conference on ASIC, 2019

Temperature Dependence of Bias Temperature Instability (BTI) in Long-term Measurement by BTI-sensitive and -insensitive Ring Oscillators Removing Environmental Fluctuation.
Proceedings of the 13th IEEE International Conference on ASIC, 2019

2018
A Low-Power Radiation-Hardened Flip-Flop with Stacked Transistors in a 65 nm FDSOI Process.
IEICE Trans. Electron., 2018

Sensitivity to soft errors of NMOS and PMOS transistors evaluated by latches with stacking structures in a 65 nm FDSOI process.
Proceedings of the IEEE International Reliability Physics Symposium, 2018

2017
Replication of Random Telegraph Noise by Using a Physical-Based Verilog-AMS Model.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2017

Circuit-level simulation methodology for Random Telegraph Noise by using Verilog-AMS.
Proceedings of the 2017 IEEE International Conference on IC Design and Technology, 2017

Highly-reliable integrated circuits for Gro.
Proceedings of the 12th IEEE International Conference on ASIC, 2017

2016
Size Optimization Technique for Logic Circuits that Considers BTI and Process Variations.
IPSJ Trans. Syst. LSI Des. Methodol., 2016

2015
A Perpetuum Mobile 32bit CPU on 65nm SOTB CMOS Technology with Reverse-Body-Bias Assisted Sleep Mode.
IEICE Trans. Electron., 2015

Impact of Cell Distance and Well-contact Density on Neutron-induced Multiple Cell Upsets.
IEICE Trans. Electron., 2015

Negative bias temperature instability caused by plasma induced damage in 65 nm bulk and Silicon on thin BOX (SOTB) processes.
Proceedings of the IEEE International Reliability Physics Symposium, 2015

Impact of random telegraph noise on ring oscillators evaluated by circuit-level simulations.
Proceedings of the 2015 International Conference on IC Design & Technology, 2015

Reliability-configurable mixed-grained reconfigurable array compatible with high-level synthesis.
Proceedings of the 20th Asia and South Pacific Design Automation Conference, 2015

2014
Correlations between BTI-Induced Degradations and Process Variations on ASICs and FPGAs.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2014

Reliability-Configurable Mixed-Grained Reconfigurable Array Supporting C-Based Design and Its Irradiation Testing.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2014

Foreword.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2014

A Perpetuum Mobile 32bit CPU with 13.4pJ/cycle, 0.14µA sleep current using Reverse Body Bias Assisted 65nm SOTB CMOS technology.
Proceedings of the 2014 IEEE Symposium on Low-Power and High-Speed Chips, 2014

Impact of random telegraph noise on CMOS logic circuit reliability.
Proceedings of the IEEE 2014 Custom Integrated Circuits Conference, 2014

2013
A Radiation-Hard Redundant Flip-Flop to Suppress Multiple Cell Upset by Utilizing the Parasitic Bipolar Effect.
IEICE Trans. Electron., 2013

2012
NBTI-Induced Delay Degradation Analysis of FPGA Routing Structures.
IPSJ Trans. Syst. LSI Des. Methodol., 2012

2011
Variation-Tolerance of a 65-nm Error-Hardened Dual-Modular-Redundancy Flip-Flop Measured by Shift-Register-Based Monitor Structures.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2011

Modeling of Random Telegraph Noise under circuit operation - Simulation and measurement of RTN-induced delay fluctuation.
Proceedings of the 12th International Symposium on Quality Electronic Design, 2011

Correlations between well potential and SEUs measured by well-potential perturbation detectors in 65nm.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2011

A 65nm flip-flop array to measure soft error resiliency against high-energy neutron and alpha particles.
Proceedings of the 16th Asia South Pacific Design Automation Conference, 2011

2010
Effect of Regularity-Enhanced Layout on Variability and Circuit Performance of Standard Cells.
IPSJ Trans. Syst. LSI Des. Methodol., 2010

An Area/Delay Efficient Dual-Modular Flip-Flop with Higher SEU/SET Immunity.
IEICE Trans. Electron., 2010

A Minimal Roll-Back Based Recovery Scheme for Fault Toleration in Pipeline Processors.
Proceedings of the 16th IEEE Pacific Rim International Symposium on Dependable Computing, 2010

A Stage-Level Recovery Scheme in Scalable Pipeline Modules for High Dependability.
Proceedings of the International Workshop on Innovative Architecture for Future Generation High Performance Processors and Systems, 2010

Evaluation of FPGA design guardband caused by inhomogeneous NBTI degradation considering process variations.
Proceedings of the International Conference on Field-Programmable Technology, 2010

2009
Erect of regularity-enhanced layout on printability and circuit performance of standard cells.
Proceedings of the 10th International Symposium on Quality of Electronic Design (ISQED 2009), 2009

2008
Performance optimization by track swapping on critical paths utilizing random variations for FPGAS.
Proceedings of the FPL 2008, 2008

A variation-aware constant-order optimization scheme utilizing delay detectors to search for fastest paths on FPGAS.
Proceedings of the FPL 2008, 2008

Speed and yield enhancement by track swapping on critical paths utilizing random variations for FPGAs.
Proceedings of the ACM/SIGDA 16th International Symposium on Field Programmable Gate Arrays, 2008

Best ways to use billions of devices on a chip - Error predictive, defect tolerant and error recovery designs.
Proceedings of the 13th Asia South Pacific Design Automation Conference, 2008

2007
A 90 nm 48 x 48 LUT-Based FPGA Enhancing Speed and Yield Utilizing Within-Die Delay Variations.
IEICE Trans. Electron., 2007

A 90 nm LUT Array for Speed and Yield Enhancement by Utilizing Within-Die Delay Variations.
IEICE Trans. Electron., 2007

A 90nm 8×16 FPGA Enhancing Speed and Yield Utilizing Within-Die Variations.
Proceedings of the 12th Conference on Asia South Pacific Design Automation, 2007

2006
Alternate Self-Shielding for High-Speed and Reliable On-Chip Global Interconnect.
IEICE Trans. Electron., 2006

A Leakage Reduction Scheme for Sleep Transistors with Decoupling Capacitors in the Deep Submicron Era.
IEICE Trans. Electron., 2006

A Yield and Speed Enhancement Technique Using Reconfigurable Devices Against Within-Die Variations on the Nanometer Regime.
Proceedings of the 2006 International Conference on Field Programmable Logic and Applications (FPL), 2006

Measurement results of within-die variations on a 90nm LUT array for speed and yield enhancement of reconfigurable devices.
Proceedings of the 2006 Conference on Asia South Pacific Design Automation: ASP-DAC 2006, 2006

2005
A Resource-Shared VLIW Processor for Low-Power On-Chip Multiprocessing in the Nanometer Era.
IEICE Trans. Electron., 2005

A yield and speed enhancement scheme under within-die variations on 90nm LUT array.
Proceedings of the IEEE 2005 Custom Integrated Circuits Conference, 2005

A resource-shared VLIW processor architecture for area-efficient on-chip multiprocessing.
Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005

2004
A Comprehensive Simulation and Test Environment for Prototype VLSI Verification.
IEICE Trans. Inf. Syst., 2004

RTL/ISS co-modeling methodology for embedded processor using SystemC.
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004

An SoC architecture and its design methodology using unifunctional heterogeneous processor array.
Proceedings of the 2004 Conference on Asia South Pacific Design Automation: Electronic Design and Solution Fair 2004, 2004

2002
Measurement results of on-chip IR-drop.
Proceedings of the IEEE 2002 Custom Integrated Circuits Conference, 2002

2001
ST: PERL package for simulation and test environment.
Proceedings of the 2001 International Symposium on Circuits and Systems, 2001

A vector-pipeline DSP for low-rate videophones.
Proceedings of ASP-DAC 2001, 2001

1998
Real time low bit-rate video coding algorithm using multi-stage hierarchical vector quantization.
Proceedings of the 1998 IEEE International Conference on Acoustics, 1998

1997
A functional memory type parallel processor for vector quantization.
Proceedings of the ASP-DAC '97 Asia and South Pacific Design Automation Conference, 1997


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