Kenshu Seto

According to our database, Kenshu Seto authored at least 25 papers between 2002 and 2025.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2025

Scalar Replacement in the Presence of Multiple Write Accesses with Non-constant Reuse Distances.

Kenshu Seto

IPSJ Trans. Syst. LSI Des. Methodol., 2025

Proposal for Non-Volatilization of Logic Cell Architecture for eFPGA IP.

Keizo Hiraga, Kenshu Seto, Kazuhiro Bessho, Masahiro Iida

IPSJ Trans. Syst. LSI Des. Methodol., 2025

Enhancing FPGA Routing Efficiency with Graph Neural Network-Based Congestion Prediction.

Kazuki Tokuishi, Motoki Amagasaki, Masato Kiyama, Kenshu Seto

Proceedings of the 15th International Symposium on Highly Efficient Accelerators and Reconfigurable Technologies, 2025

Minimizing Local Interconnections to Reduce Chip Area in eFPGAs.

Kenshu Seto, Masahiro Iida

Proceedings of the 15th International Symposium on Highly Efficient Accelerators and Reconfigurable Technologies, 2025

Proposal for Non-Volatilization of eFPGA Core.

Keizo Hiraga, Kenshu Seto, Kazuhiro Bessho, Masahiro Iida

Proceedings of the IEEE Symposium on Low-Power and High-Speed Chips and Systems, 2025

2021

Scalar replacement in the presence of multiple write accesses for high-level synthesis.

Kenshu Seto

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2021

2020

Shift Register Initialization in Scalar Replacement for Reducing Code Size.

Kenshu Seto

IPSJ Trans. Syst. LSI Des. Methodol., 2020

2019

Scalar Replacement with Circular Buffers.

Kenshu Seto

IPSJ Trans. Syst. LSI Des. Methodol., 2019

Small Memory Footprint Neural Network Accelerators.

Kenshu Seto, Hamid Nejatollahi, Jiyoung An, Sujin Kang, Nikil D. Dutt

Proceedings of the 20th International Symposium on Quality Electronic Design, 2019

2018

Scalar Replacement with Polyhedral Model.

Kenshu Seto

IPSJ Trans. Syst. LSI Des. Methodol., 2018

2014

Forwarding Unit Generation for Loop Pipelining in High-level Synthesis.

Shingo Kusakabe, Kenshu Seto

IPSJ Trans. Syst. LSI Des. Methodol., 2014

2013

Loop Fusion with Outer Loop Shifting for High-level Synthesis.

Yuta Kato, Kenshu Seto

IPSJ Trans. Syst. LSI Des. Methodol., 2013

2010

Custom Instruction Generation for Configurable Processors with Limited Numbers of Operands.

Kenshu Seto, Masahiro Fujita

IPSJ Trans. Syst. LSI Des. Methodol., 2010

2009

Interconnect-Aware Pipeline Synthesis for Array-Based Architectures.

Shanghua Gao, Hiroaki Yoshida, Kenshu Seto, Satoshi Komatsu, Masahiro Fujita

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2009

2008

Dependence Graph Based Verification and Synthesis of Hardware/Software Co-Designs with SAT Related Formulation.

Masahiro Fujita, Kenshu Seto, Thanyapat Sakunkonchak

J. Satisf. Boolean Model. Comput., 2008

Custom Instruction Generation with High-Level Synthesis.

Kenshu Seto, Masahiro Fujita

Proceedings of the IEEE Symposium on Application Specific Processors, 2008

SAT-based resource binding for reducing critical path delays.

Kenshu Seto, Yuta Nonaka, Takuya Maruizumi, Yasuhiro Shiraki

Proceedings of the FPL 2008, 2008

2007

Interconnect-aware Pipeline Synthesis for Array based Reconfigurable Architectures.

Shanghua Gao, Kenshu Seto, Satoshi Komatsu, Masahiro Fujita

Proceedings of the Embedded System Design: Topics, Techniques and Trends, IFIP TC10 Working Conference: International Embedded Systems Symposium (IESS), May 30, 2007

Protocol Transducer Synthesis using Divide and Conquer approach.

Shigeru Watanabe, Kenshu Seto, Yuji Ishikawa, Satoshi Komatsu, Masahiro Fujita

Proceedings of the 12th Conference on Asia South Pacific Design Automation, 2007

2006

Dynamically reconfigurable protocol transducer.

Shota Watanabe, Yuji Ishikawa, Kenshu Seto, Satoshi Komatsu, Masahiro Fujita

Proceedings of the 2006 IEEE International Conference on Field Programmable Technology, 2006

2005

Pipeline Scheduling for Array Based Reconfigurable Architectures Considering Interconnect Delays.

Shanghua Gao, Kenshu Seto, Satoshi Komatsu, Masahiro Fujita

Proceedings of the 2005 IEEE International Conference on Field-Programmable Technology, 2005

2003

Engineering Changes in Field Modifiable Architectures.

Hiroshi Saito, Kenshu Seto, Yoshihisa Kojima, Satoshi Komatsu, Masahiro Fujita

Proceedings of the 1st ACM & IEEE International Conference on Formal Methods and Models for Co-Design (MEMOCODE 2003), 2003

Field Modifiable Architecture with FPGAs and its Design/Verification/Debugging Methodologies.

Masahiro Fujita, Satoshi Komatsu, Hiroshi Saito, Kenshu Seto, Thanyapat Sakunkonchak, Yoshihisa Kojima

Proceedings of the 36th Hawaii International Conference on System Sciences (HICSS-36 2003), 2003

2002

Field Modifiable Architecture and its Design Methodology: System Design Without Logic Synthesis.

Yoshihisa Kojima, Hiroshi Saito, Kenshu Seto, Satoshi Komatsu, Masahiro Fujita

Proceedings of the 11th IEEE/ACM International Workshop on Logic & Synthesis, 2002

Field modifiable architecture with FPGAs and its design methodology.

Satoshi Komatsu, Yoshihisa Kojima, Hiroshi Saito, Kenshu Seto, Masahiro Fujita

Proceedings of the 2002 IEEE International Conference on Field-Programmable Technology, 2002