Keizo Hiraga

According to our database, Keizo Hiraga authored at least 10 papers between 2000 and 2024.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of three.

2024

Optimized Two-Step Store Control for MTJ-Based Nonvolatile Flip-Flops to Minimize Store Energy Under Process and Temperature Variations.

Kimiyoshi Usami, Daiki Yokoyama, Aika Kamei, Hideharu Amano, Kenta Suzuki, Keizo Hiraga, Kazuhiro Bessho

IEEE Trans. Very Large Scale Integr. Syst., January, 2024

2023

A Variation-Aware MTJ Store Energy Estimation Model for Edge Devices With Verify-and-Retryable Nonvolatile Flip-Flops.

Aika Kamei, Hideharu Amano, Takuya Kojima, Daiki Yokoyama, Kimiyoshi Usami, Keizo Hiraga, Kenta Suzuki, Kazuhiro Bessho

IEEE Trans. Very Large Scale Integr. Syst., April, 2023

A 40 nm 2 kb MTJ-Based Non-Volatile SRAM Macro with Novel Data-Aware Store Architecture for Normally Off Computing.

Kenta Suzuki, Keizo Hiraga, Kazuhiro Bessho, Kimiyoshi Usami, Taku Umebayashi

Proceedings of the 2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), 2023

A Non-stop Fault-Tolerant Real-Time System-on-Chip/System-in-Package.

Shota Nakabeppu, Nobuyuki Yamasaki, Kenta Suzuki, Keizo Hiraga, Kazuhiro Bessho

Proceedings of the Eleventh International Symposium on Computing and Networking, CANDAR 2023, Matsue, Japan, November 28, 2023

2021

Energy saving in a multi-context coarse grained reconfigurable array with non-volatile flip-flops.

Aika Kamei, Takuya Kojima, Hideharu Amano, Daiki Yokoyama, Hisato Miyauchi, Kimiyoshi Usami, Keizo Hiraga, Kenta Suzuki, Kazuhiro Bessho

Proceedings of the 14th IEEE International Symposium on Embedded Multicore/Many-core Systems-on-Chip, 2021

2020

Non-Volatile Coarse Grained Reconfigurable Array Enabling Two-step Store Control for Energy Minimization.

Kimiyoshi Usami, Sosuke Akiba, Hideharu Amano, Takeharu Ikezoe, Keizo Hiraga, Kenta Suzuki, Yasuo Kanda

Proceedings of the 2020 IEEE Symposium in Low-Power and High-Speed Chips, 2020

2018

A Coarse Grained-Reconfigurable Accelerator with energy efficient MTJ-based Non-volatile Flip-flops.

Takeharu Ikezoe, Hideharu Amano, Junya Akaike, Kimiyoshi Usami, Masaru Kudo, Keizo Hiraga, Yusuke Shuto, Kojiro Yagami

Proceedings of the 2018 International Conference on ReConFigurable Computing and FPGAs, 2018

Energy Efficient Write Verify and Retry Scheme for MTJ Based Flip-Flop and Application.

Kimiyoshi Usami, Junya Akaike, Sosuke Akiba, Masaru Kudo, Hideharu Amano, Takeharu Ikezoe, Keizo Hiraga, Yusuke Shuto, Kojiro Yagami

Proceedings of the IEEE 7th Non-Volatile Memory Systems and Applications Symposium, 2018

2015

Impact of fin shape variability on device performance towards 10nm node.

Kazuyuki Tomida, Keizo Hiraga, Morin Dehan, Geert Hellings, Doyoung Jang, Kenichi Miyaguchi, Thomas Chiarella, Minsoo Kim, Anda Mocuta, Naoto Horiguchi, Abdelkarim Mercha, Diederik Verkest, Aaron Thean

Proceedings of the 2015 International Conference on IC Design & Technology, 2015

2000

A 144-Mb, eight-level NAND flash memory with optimized pulsewidth programming.

Hiromi Nobukata, Shunsuke Takagi, Keizo Hiraga, Takeshi Ohgishi, Masaru Miyashita, Kazuto Kamimura, Shinji Hiramatsu, Kiyohisa Sakai, Takahiro Ishida, Hideki Arakawa, Masahiko Itoh, Ihachi Naiki, Masanori Noda

IEEE J. Solid State Circuits, 2000