Kenshu Seto

According to our database1, Kenshu Seto authored at least 20 papers between 2002 and 2021.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

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PhD thesis 
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Links

On csauthors.net:

Bibliography

2021
Scalar replacement in the presence of multiple write accesses for high-level synthesis.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2021

2020
Shift Register Initialization in Scalar Replacement for Reducing Code Size.
IPSJ Trans. Syst. LSI Des. Methodol., 2020

2019
Scalar Replacement with Circular Buffers.
IPSJ Trans. Syst. LSI Des. Methodol., 2019

Small Memory Footprint Neural Network Accelerators.
Proceedings of the 20th International Symposium on Quality Electronic Design, 2019

2018
Scalar Replacement with Polyhedral Model.
IPSJ Trans. Syst. LSI Des. Methodol., 2018

2014
Forwarding Unit Generation for Loop Pipelining in High-level Synthesis.
IPSJ Trans. Syst. LSI Des. Methodol., 2014

2013
Loop Fusion with Outer Loop Shifting for High-level Synthesis.
IPSJ Trans. Syst. LSI Des. Methodol., 2013

2010
Custom Instruction Generation for Configurable Processors with Limited Numbers of Operands.
IPSJ Trans. Syst. LSI Des. Methodol., 2010

2009
Interconnect-Aware Pipeline Synthesis for Array-Based Architectures.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2009

2008
Dependence Graph Based Verification and Synthesis of Hardware/Software Co-Designs with SAT Related Formulation.
J. Satisf. Boolean Model. Comput., 2008

Custom Instruction Generation with High-Level Synthesis.
Proceedings of the IEEE Symposium on Application Specific Processors, 2008

SAT-based resource binding for reducing critical path delays.
Proceedings of the FPL 2008, 2008

2007
Interconnect-aware Pipeline Synthesis for Array based Reconfigurable Architectures.
Proceedings of the Embedded System Design: Topics, Techniques and Trends, IFIP TC10 Working Conference: International Embedded Systems Symposium (IESS), May 30, 2007

Protocol Transducer Synthesis using Divide and Conquer approach.
Proceedings of the 12th Conference on Asia South Pacific Design Automation, 2007

2006
Dynamically reconfigurable protocol transducer.
Proceedings of the 2006 IEEE International Conference on Field Programmable Technology, 2006

2005
Pipeline Scheduling for Array Based Reconfigurable Architectures Considering Interconnect Delays.
Proceedings of the 2005 IEEE International Conference on Field-Programmable Technology, 2005

2003
Engineering Changes in Field Modifiable Architectures.
Proceedings of the 1st ACM & IEEE International Conference on Formal Methods and Models for Co-Design (MEMOCODE 2003), 2003

Field Modifiable Architecture with FPGAs and its Design/Verification/Debugging Methodologies.
Proceedings of the 36th Hawaii International Conference on System Sciences (HICSS-36 2003), 2003

2002
Field Modifiable Architecture and its Design Methodology: System Design Without Logic Synthesis.
Proceedings of the 11th IEEE/ACM International Workshop on Logic & Synthesis, 2002

Field modifiable architecture with FPGAs and its design methodology.
Proceedings of the 2002 IEEE International Conference on Field-Programmable Technology, 2002


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