Khai-Duy Nguyen

Orcid: 0000-0003-3623-5250

Affiliations:
  • University of Electro-Communications, Tokyo, Japan


According to our database1, Khai-Duy Nguyen authored at least 23 papers between 2020 and 2025.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

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Bibliography

2025
A Unified Approach to Strong PUF and TRNG Using Ring Generator for Cryptography.
IEEE Internet Things J., September, 2025

ASIC Implementation of ASCON Lightweight Cryptography for IoT Applications.
IEEE Trans. Circuits Syst. II Express Briefs, January, 2025

An Area-Time Efficient Hardware Architecture for ML-KEM Post-Quantum Cryptography Standard.
IEEE Access, 2025

Live Demonstration: ASIC Implementation of ASCON Lightweight Cryptography for IoT Applications.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2025

Dual-Mode PUF and TRNG Design with Ring Generator on 180nm CMOS.
Proceedings of the International Conference on IC Design and Technology, 2025

2024
Accumulator-Based 16-Bit Processor for Wireless Sensor Nodes.
IEEE Trans. Circuits Syst. II Express Briefs, July, 2024

Realization of Authenticated One-Pass Key Establishment on RISC-V Micro-Controller for IoT Applications.
Future Internet, May, 2024

Hardware Software Co-Design for Multi-Threaded Computation on RISC-V-Based Multicore System.
IEEE Access, 2024

A Resource-Efficient Multi-core Multi-thread RISC-V-based System-on-Chip.
Proceedings of the 21st International SoC Design Conference, 2024

A Unified OTP and PUF Exploiting Post-Program Current on Standard CMOS Technology.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2024

RISC-V-Based System-on-Chips for IoT Applications.
Proceedings of the 36th IEEE Hot Chips Symposium, 2024

A Trusted Execution Environment RISC-V System on Chip.
Proceedings of the 36th IEEE Hot Chips Symposium, 2024

2022
Systems on a Chip With 8 and 32 Bits Processors in 0.18-μm Technology for IoT Applications.
IEEE Trans. Circuits Syst. II Express Briefs, 2022

Trusted Execution Environment Hardware by Isolated Heterogeneous Architecture for Key Scheduling.
IEEE Access, 2022

A System-on-Chip for IoT Applications with 16-bit Tiny Processor.
Proceedings of the International Conference on IC Design and Technology, 2022

2021
A Sub-μ W Reversed-Body-Bias 8-bit Processor on 65-nm Silicon-on-Thin-Box (SOTB) for IoT Applications.
IEEE Trans. Circuits Syst. II Express Briefs, 2021

A trigonometric hardware acceleration in 32-bit RISC-V microcontroller with custom instruction.
IEICE Electron. Express, 2021

A proposal for enhancing training speed in deep learning models based on memory activity survey.
IEICE Electron. Express, 2021

A Fully Digital True Random Number Generator With Entropy Source Based in Frequency Collapse.
IEEE Access, 2021

A Low-Power Low-Area SoC based in RISC-V Processor for IoT Applications.
Proceedings of the 18th International SoC Design Conference, 2021

A CORDIC-based Trigonometric Hardware Accelerator with Custom Instruction in 32-bit RISC-V System-on-Chip.
Proceedings of the IEEE Hot Chips 33 Symposium, 2021

System-on-Chip Implementation of Trusted Execution Environment with Heterogeneous Architecture.
Proceedings of the IEEE Hot Chips 33 Symposium, 2021

2020
Low-power high-performance 32-bit RISC-V microcontroller on 65-nm silicon-on-thin-BOX (SOTB).
IEICE Electron. Express, 2020


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