Akira Tsukamoto

Orcid: 0000-0002-3339-7177

According to our database1, Akira Tsukamoto authored at least 24 papers between 2005 and 2023.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Links

On csauthors.net:

Bibliography

2023
A cross-process Spectre attack via cache on RISC-V processor with trusted execution environment.
Comput. Electr. Eng., January, 2023

2022
A Robust and Healthy Against PVT Variations TRNG Based on Frequency Collapse.
IEEE Access, 2022

Trusted Execution Environment Hardware by Isolated Heterogeneous Architecture for Key Scheduling.
IEEE Access, 2022

High-performance Multi-function HMAC-SHA2 FPGA Implementation.
Proceedings of the 20th IEEE Interregional NEWCAS Conference, 2022

Spectre attack detection with Neutral Network on RISC-V processor.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2022

2021
TS-Perf: General Performance Measurement of Trusted Execution Environment and Rich Execution Environment on Intel SGX, Arm TrustZone, and RISC-V Keystone.
IEEE Access, 2021

A Fully Digital True Random Number Generator With Entropy Source Based in Frequency Collapse.
IEEE Access, 2021

A Real-Time Cache Side-Channel Attack Detection System on RISC-V Out-of-Order Processor.
IEEE Access, 2021

Correlation Power Analysis Attack Resisted Cryptographic RISC-V SoC With Random Dynamic Frequency Scaling Countermeasure.
IEEE Access, 2021

Exploiting the Back-Gate Biasing Technique as a Countermeasure Against Power Analysis Attacks.
IEEE Access, 2021

ChaCha20-Poly1305 Crypto Core Compatible with Transport Layer Security 1.3.
Proceedings of the 18th International SoC Design Conference, 2021

System-on-Chip Implementation of Trusted Execution Environment with Heterogeneous Architecture.
Proceedings of the IEEE Hot Chips 33 Symposium, 2021

2020
An in vitro model of temporal enhancement of epithelium barrier permeability by low-energy shock waves without contrast agents.
Medical Biol. Eng. Comput., 2020

Low-power high-performance 32-bit RISC-V microcontroller on 65-nm silicon-on-thin-BOX (SOTB).
IEICE Electron. Express, 2020

Quick Boot of Trusted Execution Environment With Hardware Accelerators.
IEEE Access, 2020

Library Implementation and Performance Analysis of GlobalPlatform TEE Internal API for Intel SGX and RISC-V Keystone.
Proceedings of the 19th IEEE International Conference on Trust, 2020

Cryptographic Accelerators for Trusted Execution Environment in RISC-V Processors.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2020

Reboot-Oriented IoT: Life Cycle Management in Trusted Execution Environment for Disposable IoT devices.
Proceedings of the ACSAC '20: Annual Computer Security Applications Conference, 2020

2018
Analysis of Dielectrophoretic Properties of Cells by the use of the Uniform Field Gradient.
Proceedings of the 2018 World Automation Congress, 2018

A two-stage-pipeline CPU of SH-2 architecture implemented on FPGA and SoC for IoT, edge AI and robotic applications.
Proceedings of the 2018 IEEE Symposium in Low-Power and High-Speed Chips, 2018

2012
Recent Developments of High-<i>T<sub>c</sub></i> Electronic Devices with Multilayer Structures and Ramp-Edge Josephson Junctions.
IEICE Trans. Electron., 2012

2009
Liquid-Phase Detection of Biological Targets with Magnetic Marker and Superconducting Quantum Interference Device.
IEICE Trans. Electron., 2009

2005
Magnetic Marker and High <i>T<sub>c</sub></i> Superconducting Quantum Interference Device for Biological Immunoassays.
IEICE Trans. Electron., 2005

Scalable Overlay Network Deployment for Dynamic Collaborative Groups.
Proceedings of the 2005 IEEE/IPSJ International Symposium on Applications and the Internet (SAINT 2005), 31 January, 2005


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