Van-Phuc Hoang
Orcid: 0000-0003-0944-8701
According to our database1,
Van-Phuc Hoang
authored at least 43 papers
between 2011 and 2024.
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Bibliography
2024
IEEE Trans. Very Large Scale Integr. Syst., March, 2024
2023
Transition Factors of Power Consumption Models for CPA Attacks on Cryptographic RISC-V SoC.
IEEE Trans. Computers, September, 2023
Efficient Nonprofiled Side-Channel Attack Using Multi-Output Classification Neural Network.
IEEE Embed. Syst. Lett., September, 2023
A low-power charge-based integrate-and-fire circuit for binarized-spiking neural network.
Int. J. Circuit Theory Appl., July, 2023
On the performance of non-profiled side channel attacks based on deep learning techniques.
IET Inf. Secur., May, 2023
Proceedings of the IEEE Statistical Signal Processing Workshop, 2023
Proceedings of the IEEE Statistical Signal Processing Workshop, 2023
An Efficient Deep Network for Modulation Classification in Impaired MIMO-OFDM Systems.
Proceedings of the IEEE Statistical Signal Processing Workshop, 2023
Proceedings of the 16th IEEE International Symposium on Embedded Multicore/Many-core Systems-on-Chip, 2023
Dynamic Gold Code-Based Chaotic Clock for Cryptographic Designs to Counter Power Analysis Attacks.
Proceedings of the Great Lakes Symposium on VLSI 2023, 2023
2022
A Cost-Effective 5-W GaN HEMT Power Amplifier for Sub-6-GHz 5G Wireless Communications.
Mob. Networks Appl., 2022
Integr., 2022
MoDANet: Multi-Task Deep Network for Joint Automatic Modulation Classification and Direction of Arrival Estimation.
IEEE Commun. Lett., 2022
Low Complexity Correlation Power Analysis by Combining Power Trace Biasing and Correlation Distribution Techniques.
IEEE Access, 2022
Performance Analysis of Convolutional Neural Networks with Different Window Functions for Automatic Modulation Classification.
Proceedings of the 13th International Conference on Information and Communication Technology Convergence, 2022
Proceedings of the International Conference on IC Design and Technology, 2022
Proceedings of the International Conference on IC Design and Technology, 2022
2021
A Sub-μ W Reversed-Body-Bias 8-bit Processor on 65-nm Silicon-on-Thin-Box (SOTB) for IoT Applications.
IEEE Trans. Circuits Syst. II Express Briefs, 2021
Convergence of 5G Technologies, Artificial Intelligence and Cybersecurity of Networked Societies for the Cities of Tomorrow.
Mob. Networks Appl., 2021
Hardware Trojan Detection Based on Side-Channel Analysis Using Power Traces and Machine Learning.
Proceedings of the Sixth International Conference on Research in Intelligent and Computing, 2021
Proceedings of the International Conference on Information and Communication Technology Convergence, 2021
2020
Linearization of RF Power Amplifiers in Wideband Communication Systems by Adaptive Indirect Learning Using RPEM Algorithm.
Mob. Networks Appl., 2020
Convolutional Neural Network-Based DOA Estimation Using Non-uniform Linear Array for Multipath Channels.
Proceedings of the Industrial Networks and Intelligent Systems, 2020
Proceedings of the Industrial Networks and Intelligent Systems, 2020
Low-Power Implementation of a High-Throughput Multi-core AES Encryption Architecture.
Proceedings of the 2020 IEEE Asia Pacific Conference on Circuits and Systems, 2020
Performance Analysis of Non-Profiled Side Channel Attacks Based on Convolutional Neural Networks.
Proceedings of the 2020 IEEE Asia Pacific Conference on Circuits and Systems, 2020
2019
All-Digital Background Calibration Technique for Offset, Gain and Timing Mismatches in Time-Interleaved ADCs.
EAI Endorsed Trans. Ind. Networks Intell. Syst., 2019
Proceedings of the 13th IEEE International Symposium on Embedded Multicore/Many-core Systems-on-Chip, 2019
A 1.2-V 90-MHz Bitmap Index Creation Accelerator with 0.27-nW Standby Power on 65-nm Silicon-On-Thin-Box (SOTB) CMOS.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2019
Live Demonstration: Real-Time Auto-Exposure Histogram Equalization Video-System using Frequent Items Counter.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2019
Proceedings of the Industrial Networks and Intelligent Systems, 2019
2018
An Efficient Hardware Implementation of Activation Functions Using Stochastic Computing for Deep Neural Networks.
Proceedings of the 12th IEEE International Symposium on Embedded Multicore/Many-core Systems-on-Chip, 2018
Hardware Implementation of Background Calibration Technique for TIADCs with Signals in Any Nyquist Bands.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018
2017
A new approach of stochastic computing for arithmetic functions in wideband RF transceivers.
Proceedings of the IEEE 60th International Midwest Symposium on Circuits and Systems, 2017
Proceedings of the IEEE 60th International Midwest Symposium on Circuits and Systems, 2017
2016
Proceedings of the 2016 IFIP/IEEE International Conference on Very Large Scale Integration, 2016
Proceedings of the International SoC Design Conference, 2016
Proceedings of the International Conference on IC Design and Technology, 2016
2013
Low Complexity Logarithmic and Anti-Logarithmic Converters for Hybrid Number System Processors and DSP Applications.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2013
2012
An Improved Hybrid LUT-Based Architecture for Low-Error and Efficient Fixed-Width Squarer.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2012
Efficient LUT-Based Truncated Multiplier and Its Application in RGB to YCbCr Color Space Conversion.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2012
2011
An Improved Linear Difference Method with High ROM Compression Ratio in Direct Digital Frequency Synthesizer.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2011