Kimihiko Kato

According to our database, Kimihiko Kato authored at least 9 papers between 2018 and 2024.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of five.

2024

Temperature Dependent Variations of Low-Frequency Noise Sources in Cryogenic Short-Channel Bulk MOSFETs.

Takumi Inaba, Hiroshi Oka, Hidehiro Asai, Hiroshi Fuketa, Shota Iizuka, Kimihiko Kato, Shunsuke Shitakata, Koichi Fukuda, Takahiro Mori

IEEE Access, 2024

2023

Single-Electron Transistor Operation of a Physically Defined Silicon Quantum Dot Device Fabricated by Electron Beam Lithography Employing a Negative-Tone Resist.

Shimpei Nishiyama, Kimihiko Kato, Yongxun Liu, Raisei Mizokuchi, Jun Yoneda, Tetsuo Kodera, Takahiro Mori

IEICE Trans. Electron., October, 2023

Origin of Low-Frequency Noise in Si n-MOSFET at Cryogenic Temperatures: The Effect of Interface Quality.

Hiroshi Oka, Takumi Inaba, Shunsuke Shitakata, Kimihiko Kato, Shota Iizuka, Hidehiro Asai, Hiroshi Fuketa, Takahiro Mori

IEEE Access, 2023

Determining the low-frequency noise source in cryogenic operation of short-channel bulk MOSFETs.

Takumi Inaba, Hiroshi Oka, Hidehiro Asai, Hiroshi Fuketa, Shota Iizuka, Kimihiko Kato, Shunsuke Shitakata, Koichi Fukuda, Takahiro Mori

Proceedings of the 2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), 2023

2022

Effect of Conduction Band Edge States on Coulomb-Limiting Electron Mobility in Cryogenic MOSFET Operation.

Hiroshi Oka, Takumi Inaba, Shota Iizuka, Hidehiro Asai, Kimihiko Kato, Takahiro Mori

Proceedings of the IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits 2022), 2022

2021

Buried nanomagnet realizing high-speed/low-variability silicon spin qubits: implementable in error-correctable large-scale quantum computers.

Shota Iizuka, Kimihiko Kato, Atsushi Yagishita, Hidehiro Asai, Tetsuya Ueda, Hiroshi Oka, Junichi Hattori, Tsutomu Ikegami, Koichi Fukuda, Takahiro Mori

Proceedings of the 2021 Symposium on VLSI Circuits, Kyoto, Japan, June 13-19, 2021, 2021

2019

Advanced MOS Device Technology for Low Power Logic LSI.

Shinichi Takagi, Kimihiko Kato, Kei Sumita, Kwangwon Jo, Cheol-Min Lim, Ryotaro Takaguchi, Dae-Hwan Ahn, Jun Takeyasu, Kasidit Toprasertpong, Mitsuru Takenaka

Proceedings of the 26th International Conference on Mixed Design of Integrated Circuits and Systems, 2019

Fabrication of High Quality InAs-on-Lnsulator Structures by Smart Cut Process with Reuse of InAs Wafers.

Kei Sumita, Jun Takeyasu, Kimihiko Kato, Kasidit Toprasertpong, Mitsuru Takenaka, Shinichi Takagi

Proceedings of the 2019 International 3D Systems Integration Conference (3DIC), 2019

2018

MOS Device Technology using Alternative Channel Materials for Low Power Logic LSI.

Shinichi Takagi, Kimihiko Kato, Wu-Kang Kim, Kwangwon Jo, Ryo Matsumura, Ryotaro Takaguchi, Dae-Hwan Ahn, Takahiro Gotow, Mitsuru Takenaka

Proceedings of the 48th European Solid-State Device Research Conference, 2018