Takahiro Mori
Orcid: 0000-0001-5899-1060
According to our database1,
Takahiro Mori authored at least 22 papers
between 2012 and 2026.
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Bibliography
2026
Cryogenic CMOS Microwave Signal Selector Using Dual-Stage Injection-Locked Oscillator for Frequency-Multiplexed Qubit Control System.
IEEE J. Solid State Circuits, April, 2026
On the Improvement of Gate Fidelity in Spin Qubits With Two-Level Fluctuators at Higher Temperatures.
IEEE Access, 2026
2025
A Study on the Origin of MOSFET Random Telegraph Noise Under Strong Inversion at Cryogenic Temperatures.
Proceedings of the IEEE International Reliability Physics Symposium, 2025
2024
Temperature Dependent Variations of Low-Frequency Noise Sources in Cryogenic Short-Channel Bulk MOSFETs.
IEEE Access, 2024
Proceedings of the Device Research Conference, 2024
2023
A Cryogenic CMOS Current Integrator and Correlation Double Sampling Circuit for Spin Qubit Readout.
IEEE Trans. Circuits Syst. I Regul. Pap., December, 2023
Single-Electron Transistor Operation of a Physically Defined Silicon Quantum Dot Device Fabricated by Electron Beam Lithography Employing a Negative-Tone Resist.
IEICE Trans. Electron., October, 2023
Origin of Low-Frequency Noise in Si n-MOSFET at Cryogenic Temperatures: The Effect of Interface Quality.
IEEE Access, 2023
Determining the low-frequency noise source in cryogenic operation of short-channel bulk MOSFETs.
Proceedings of the 2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), 2023
Proceedings of the International Conference on IC Design and Technology, 2023
2022
Effect of Conduction Band Edge States on Coulomb-Limiting Electron Mobility in Cryogenic MOSFET Operation.
Proceedings of the IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits 2022), 2022
A Cryogenic CMOS Current Comparator for Spin Qubit Readout Achieving Fast Readout Time and High Current Resolution.
Proceedings of the IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits 2022), 2022
2021
Buried nanomagnet realizing high-speed/low-variability silicon spin qubits: implementable in error-correctable large-scale quantum computers.
Proceedings of the 2021 Symposium on VLSI Circuits, Kyoto, Japan, June 13-19, 2021, 2021
2015
Proceedings of the 2015 IEEE International Conference on Robotics and Biomimetics, 2015
Proceedings of the 2015 International Conference on IC Design & Technology, 2015
2014
Improvement of epitaxial channel quality on heavily arsenic- and boron-doped Si surfaces and impact on tunnel FET performance.
Proceedings of the 44th European Solid State Device Research Conference, 2014
Variation behavior of tunnel-FETs originated from dopant concentration at source region and channel edge configuration.
Proceedings of the 44th European Solid State Device Research Conference, 2014
Proceedings of the IEEE/ASME International Conference on Advanced Intelligent Mechatronics, 2014
2013
Performance limit of parallel electric field tunnel FET and improvement by modified gate and channel configurations.
Proceedings of the European Solid-State Device Research Conference, 2013
Guidelines for symmetric threshold voltage in tunnel FinFETs with single and dual metal gate electrodes.
Proceedings of the European Solid-State Device Research Conference, 2013
2012
Proceedings of the Computer Vision, Imaging and Computer Graphics. Theory and Application, 2012
Shadow and Specular Removal by Photometric Linearization based on PCA with Outlier Exclusion.
Proceedings of the VISAPP 2012, 2012