Hiroshi Fuketa
Orcid: 0000-0003-0171-6679
According to our database1,
Hiroshi Fuketa
authored at least 55 papers
between 2008 and 2024.
Collaborative distances:
Collaborative distances:
Timeline
Legend:
Book In proceedings Article PhD thesis Dataset OtherLinks
On csauthors.net:
Bibliography
2024
Temperature Dependent Variations of Low-Frequency Noise Sources in Cryogenic Short-Channel Bulk MOSFETs.
IEEE Access, 2024
2023
A Cryogenic CMOS Current Integrator and Correlation Double Sampling Circuit for Spin Qubit Readout.
IEEE Trans. Circuits Syst. I Regul. Pap., December, 2023
Lookup Table-Based Computing-in-Memory Macro Approximating Dot Products Without Multiplications for Energy-Efficient CNN Inference.
IEEE Trans. Circuits Syst. I Regul. Pap., October, 2023
Origin of Low-Frequency Noise in Si n-MOSFET at Cryogenic Temperatures: The Effect of Interface Quality.
IEEE Access, 2023
Determining the low-frequency noise source in cryogenic operation of short-channel bulk MOSFETs.
Proceedings of the 2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), 2023
2022
Time-Delay-Neural-Network-Based Audio Feature Extractor for Ultra-Low Power Keyword Spotting.
IEEE Trans. Circuits Syst. II Express Briefs, 2022
A Cryogenic CMOS Current Comparator for Spin Qubit Readout Achieving Fast Readout Time and High Current Resolution.
Proceedings of the IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits 2022), 2022
2021
2020
Neural ODE with Temporal Convolution and Time Delay Neural Networks for Small-Footprint Keyword Spotting.
CoRR, 2020
2019
Ultra-low Power Human Motion Detection Sensor using Electrostatic Induction and Demonstration of Contactless Remote Light Switch.
Proceedings of the IEEE 8th Global Conference on Consumer Electronics, 2019
2018
Image-Classifier Deep Convolutional Neural Network Training by 9-bit Dedicated Hardware to Realize Validation Accuracy and Energy Efficiency Superior to the Half Precision Floating Point Format.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018
2017
IEEE Trans. Very Large Scale Integr. Syst., 2017
IEEE Trans. Circuits Syst. II Express Briefs, 2017
Fully Integrated, 100-mV Minimum Input Voltage Converter With Gate-Boosted Charge Pump Kick-Started by LC Oscillator for Energy Harvesting.
IEEE Trans. Circuits Syst. II Express Briefs, 2017
Design and Analysis of Ultra-Low Power Glitch-Free Programmable Voltage Detector Based on Multiple Voltage Copier.
IEICE Trans. Electron., 2017
Proceedings of the 2017 IEEE International Solid-State Circuits Conference, 2017
2016
Variation-Tolerant Quick-Start-Up CMOS Crystal Oscillator With Chirp Injection and Negative Resistance Booster.
IEEE J. Solid State Circuits, 2016
2015
IEEE Trans. Circuits Syst. I Regul. Pap., 2015
16.4 Energy-autonomous fever alarm armband integrating fully flexible solar cells, piezoelectric speaker, temperature detector, and 12V organic complementary FET circuits.
Proceedings of the 2015 IEEE International Solid-State Circuits Conference, 2015
Optimal design to maximize efficiency of single-inductor multiple-output buck converters in discontinuous conduction mode for IoT applications.
Proceedings of the 2015 International Conference on IC Design & Technology, 2015
248pW, 0.11mV/°C glitch-free programmable voltage detector with multiple voltage duplicator for energy harvesting.
Proceedings of the ESSCIRC Conference 2015, 2015
Proceedings of the European Conference on Circuit Theory and Design, 2015
2014
1 µm-Thickness Ultra-Flexible and High Electrode-Density Surface Electromyogram Measurement Sheet With 2 V Organic Transistors for Prosthetic Hand Control.
IEEE Trans. Biomed. Circuits Syst., 2014
Intermittent Resonant Clocking Enabling Power Reduction at Any Clock Frequency for Near/Sub-Threshold Logic Circuits.
IEEE J. Solid State Circuits, 2014
92% start-up time reduction by variation-tolerant chirp injection (CI) and negative resistance booster (NRB) in 39MHz crystal oscillator.
Proceedings of the Symposium on VLSI Circuits, 2014
Flexible, large-area, and distributed organic electronics closely contacted with skin for healthcare applications.
Proceedings of the IEEE 57th International Midwest Symposium on Circuits and Systems, 2014
30.3 Organic-transistor-based 2kV ESD-tolerant flexible wet sensor sheet for biomedical applications with wireless power and data transmission using 13.56MHz magnetic resonance.
Proceedings of the 2014 IEEE International Conference on Solid-State Circuits Conference, 2014
An 85-mV input, 50-µs startup fully integrated voltage multiplier with passive clock boost using on-chip transformers for energy harvesting.
Proceedings of the ESSCIRC 2014, 2014
2013
Minimizing Energy of Integer Unit by Higher Voltage Flip-Flop: V<sub>DDmin</sub>-Aware Dual Supply Voltage Technique.
IEEE Trans. Very Large Scale Integr. Syst., 2013
IEEE J. Solid State Circuits, 2013
Increase of Crosstalk Noise Due to Imbalanced Threshold Voltage Between nMOS and pMOS in Subthreshold Logic Circuits.
IEEE J. Solid State Circuits, 2013
Proceedings of the 5th IEEE International Workshop on Advances in Sensors and Interfaces, 2013
1µm-thickness 64-channel surface electromyogram measurement sheet with 2V organic transistors for prosthetic hand control.
Proceedings of the 2013 IEEE International Solid-State Circuits Conference, 2013
Intermittent resonant clocking enabling power reduction at any clock frequency for 0.37V 980kHz near-threshold logic circuits.
Proceedings of the 2013 IEEE International Solid-State Circuits Conference, 2013
Reducing IR drop in 3D integration to less than 1/4 using Buck Converter on Top die (BCT) scheme.
Proceedings of the International Symposium on Quality Electronic Design, 2013
Proceedings of the IEEE 10th International Conference on ASIC, 2013
2012
On-Chip Measurement System for Within-Die Delay Variation of Individual Standard Cells in 65-nm CMOS.
IEEE Trans. Very Large Scale Integr. Syst., 2012
Adaptive Performance Compensation With In-Situ Timing Error Predictive Sensors for Subthreshold Circuits.
IEEE Trans. Very Large Scale Integr. Syst., 2012
Large Within-Die Gate Delay Variations in Sub-Threshold Logic Circuits at Low Temperature.
IEEE Trans. Circuits Syst. II Express Briefs, 2012
Insole pedometer with piezoelectric energy harvester and 2V organic digital and analog circuits.
Proceedings of the 2012 IEEE International Solid-State Circuits Conference, 2012
13% Power reduction in 16b integer unit in 40nm CMOS by adaptive power supply voltage control with parity-based error prediction and detection (PEPD) and fully integrated digital LDO.
Proceedings of the 2012 IEEE International Solid-State Circuits Conference, 2012
24% Power reduction by post-fabrication dual supply voltage control of 64 voltage domains in V<sub>DDmin</sub> limited ultra low voltage logic circuits.
Proceedings of the Thirteenth International Symposium on Quality Electronic Design, 2012
Increase of crosstalk noise due to imbalanced threshold voltage between NMOS and PMOS in sub-threshold logic circuits.
Proceedings of the IEEE 2012 Custom Integrated Circuits Conference, 2012
2011
An Average-Performance-Oriented Subthreshold Processor Self-Timed by Memory Read Completion.
IEEE Trans. Circuits Syst. II Express Briefs, 2011
Investigation of determinant factors of minimum operating voltage of logic gates in 65-nm CMOS.
Proceedings of the 2011 International Symposium on Low Power Electronics and Design, 2011
12.7-times energy efficiency increase of 16-bit integer unit by power supply voltage (V<sub>DD</sub>) scaling from 1.2v to 310mv enabled by contention-less flip-flops (CLFF) and separated V<sub>DD</sub> between flip-flops and combinational logics.
Proceedings of the 2011 International Symposium on Low Power Electronics and Design, 2011
A closed-form expression for estimating minimum operating voltage (V<sub>DDmin</sub>) of CMOS logic gates.
Proceedings of the 48th Design Automation Conference, 2011
2010
Transistor Variability Modeling and its Validation With Ring-Oscillation Frequencies for Body-Biased Subthreshold Circuits.
IEEE Trans. Very Large Scale Integr. Syst., 2010
Adaptive performance control with embedded timing error predictive sensors for subthreshold circuits.
Proceedings of the 15th Asia South Pacific Design Automation Conference, 2010
2009
An Experimental Study on Body-Biasing Layout Style Focusing on Area Efficiency and Speed Controllability.
IEICE Trans. Electron., 2009
Trade-Off Analysis between Timing Error Rate and Power Dissipation for Adaptive Speed Control with Timing Error Prediction.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2009
Adaptive performance compensation with in-situ timing error prediction for subthreshold circuits.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2009
2008
Correlation verification between transistor variability model with body biasing and ring oscillation frequency in 90nm subthreshold circuits.
Proceedings of the 2008 International Symposium on Low Power Electronics and Design, 2008
Experimental study on body-biasing layout style-- negligible area overhead enables sufficient speed controllability --.
Proceedings of the 18th ACM Great Lakes Symposium on VLSI 2008, 2008