King Ho Tam

According to our database, King Ho Tam authored at least 11 papers between 2004 and 2015.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2015

Criticality-dependency-aware timing characterization and analysis.

Yu-Ming Yang, King Ho Tam, Iris Hui-Ru Jiang

Proceedings of the 52nd Annual Design Automation Conference, 2015

2014

Design and manufacturing process co-optimization in nano-technology.

Meng-Kai Hsu, Nitesh Katta, Homer Yen-Hung Lin, Keny Tzu-Hen Lin, King Ho Tam, Ken Chung-Hsing Wang

Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2014

2008

Dual-V_dd Buffer Insertion for Power Reduction.

King Ho Tam, Yu Hu, Lei He, Tom Tong Jing, Xinyi Zhang

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2008

Challenges in gate level modeling for delay and SI at 65nm and below.

Igor Keller, King Ho Tam, Vinod Kariat

Proceedings of the 45th Design Automation Conference, 2008

2007

Simultaneous Buffer Insertion and Wire Sizing Considering Systematic CMP Variation and Random L_eff Variation.

Lei He, Andrew B. Kahng, King Ho Tam, Jinjun Xiong

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2007

Fast dual-vdd buffering based on interconnect prediction and sampling.

Yu Hu, King Ho Tam, Tong Jing, Lei He

Proceedings of the Ninth International Workshop on System-Level Interconnect Prediction (SLIP 2007), 2007

2005

Simultaneous buffer insertion and wire sizing considering systematic CMP variation and random leff variation.

Lei He, Andrew B. Kahng, King Ho Tam, Jinjun Xiong

Proceedings of the 2005 International Symposium on Physical Design, 2005

Power-optimal repeater insertion considering Vdd and Vth as design freedoms.

Yu Ching Chang, King Ho Tam, Lei He

Proceedings of the 2005 International Symposium on Low Power Electronics and Design, 2005

Buffer Insertion Considering Process Variation.

Jinjun Xiong, King Ho Tam, Lei He

Proceedings of the 2005 Design, 2005

Power optimal dual-Vdd buffered tree considering buffer stations and blockages.

King Ho Tam, Lei He

Proceedings of the 42nd Design Automation Conference, 2005

2004

Leveraging Delay Slack in Flip-Flop and Buffer Insertion for Power Reduction.

Lucanus J. Simonson, King Ho Tam, Nataraj Akkiraju, Mosur Mohan, Lei He

Proceedings of the 5th International Symposium on Quality of Electronic Design (ISQED 2004), 2004