Tong Jing

Orcid: 0000-0001-9522-2252

According to our database¹, Tong Jing authored at least 32 papers between 2002 and 2019.

Collaborative distances:

Dijkstra number² of four.
Erdős number³ of three.

Timeline

Legend:

Book

In proceedings

Article

PhD thesis

Dataset

Other

Links

On csauthors.net:

Bibliography

2019

Cramér-Rao Lower Bound Analysis for Stochastic Model Based Target Parameter Estimation in Multistatic Passive Radar With Direct-Path Interference.

[BibT_eX]

[DOI]

IEEE Access, 2019

2018

PQISEM: BN's structure learning based on partial qualitative influences and SEM algorithm from missing data.

[BibT_eX]

[DOI]

Yali Lv

Jian'ai Wu

Tong Jing

Int. J. Wirel. Mob. Comput., 2018

2008

Fashion: A Fast and Accurate Solution to Global Routing Problem.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2008

2007

Fast dual-vdd buffering based on interconnect prediction and sampling.

[BibT_eX]

[DOI]

Proceedings of the Ninth International Workshop on System-Level Interconnect Prediction (SLIP 2007), 2007

Temperature aware microprocessor floorplanning considering application dependent power load.

[BibT_eX]

[DOI]

Proceedings of the 2007 International Conference on Computer-Aided Design, 2007

DpRouter: A Fast and Accurate Dynamic-Pattern-Based Global Routing Algorithm.

[BibT_eX]

[DOI]

Proceedings of the 12th Conference on Asia South Pacific Design Automation, 2007

2006

Obstacle-avoiding rectilinear minimum-delay Steiner tree construction toward IP-block-based SOC design.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. II Express Briefs, 2006

ACO-Steiner: Ant Colony Optimization Based Rectilinear Steiner Minimal Tree Algorithm.

[BibT_eX]

[DOI]

J. Comput. Sci. Technol., 2006

A coupling and crosstalk-considered timing-driven global routing algorithm for high-performance circuit design.

[BibT_eX]

[DOI]

Integr., 2006

An O(nlogn) algorithm for obstacle-avoiding routing tree construction in the lambda-geometry plane.

[BibT_eX]

[DOI]

Proceedings of the 2006 International Symposium on Physical Design, 2006

Average lengths of wire routing under M-architecture and X-architecture.

[BibT_eX]

[DOI]

S. P. Shang

Xiaodong Hu

Tong Jing

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

CDCTree: novel obstacle-avoiding routing tree construction based on current driven circuit model.

[BibT_eX]

[DOI]

Proceedings of the 2006 Conference on Asia South Pacific Design Automation: ASP-DAC 2006, 2006

DraXRouter: global routing in X-Architecture with dynamic resource assignment.

[BibT_eX]

[DOI]

Proceedings of the 2006 Conference on Asia South Pacific Design Automation: ASP-DAC 2006, 2006

2005

Spanning graph-based nonrectilinear steiner tree algorithms.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2005

Timing-Driven Global Routing with Efficient Buffer Insertion.

[BibT_eX]

[DOI]

Jingyu Xu

Xianlong Hong

Tong Jing

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2005

A Routing Paradigm with Novel Resources Estimation and Routability Models for X-Architecture Based Physical Design.

[BibT_eX]

[DOI]

Proceedings of the Embedded Computer Systems: Architectures, 2005

Obstacle-Avoiding Rectilinear Minimum-Delay Steiner Tree Construction towards IP-Block-Based SOC Design.

[BibT_eX]

[DOI]

Proceedings of the 6th International Symposium on Quality of Electronic Design (ISQED 2005), 2005

Rotational Steiner Ratio Problem Under Uniform Orientation Metrics.

[BibT_eX]

[DOI]

Songpu Shang

Xiaodong Hu

Tong Jing

Proceedings of the Discrete Geometry, 2005

The polygonal contraction heuristic for rectilinear Steiner tree construction.

[BibT_eX]

[DOI]

Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005

A Min-area Solution to Performance and RLC Crosstalk Driven Global Routing Problem.

[BibT_eX]

[DOI]

Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005

An-OARSMan: obstacle-avoiding routing tree construction with good length performance.

[BibT_eX]

[DOI]

Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005

Via-Aware Global Routing for Good VLSI Manufacturability and High Yield.

[BibT_eX]

[DOI]

Proceedings of the 16th IEEE International Conference on Application-Specific Systems, 2005

2004

UTACO: a unified timing and congestion optimization algorithm for standard cell global routing.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2004

An Efficient Low-Degree RMST Algorithm for VLSI/ULSI Physical Design.

[BibT_eX]

[DOI]

Proceedings of the Integrated Circuit and System Design, 2004

Performance and RLC crosstalk driven global routing.

[BibT_eX]

Proceedings of the 2004 International Symposium on Circuits and Systems, 2004

Efficient octilinear Steiner tree construction based on spanning graphs.

[BibT_eX]

[DOI]

Proceedings of the 2004 Conference on Asia South Pacific Design Automation: Electronic Design and Solution Fair 2004, 2004

2003

SSTT: Efficient Local Search for GSI Global Routing.

[BibT_eX]

[DOI]

J. Comput. Sci. Technol., 2003

CNB: A Critical-Network-Based Timing Optimization Method for Standard Cell Global Routing.

[BibT_eX]

[DOI]

J. Comput. Sci. Technol., 2003

An efficient hierarchical timing-driven Steiner tree algorithm for global routing.

[BibT_eX]

[DOI]

Integr., 2003

A Novel Timing-Driven Global Routing Algorithm Considering Coupling Effects for High Performance Circuit Design.

[BibT_eX]

[DOI]

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2003

UTACO: a unified timing and congestion optimizing algorithm for standard cell global routing.

[BibT_eX]

[DOI]

Proceedings of the 2003 Asia and South Pacific Design Automation Conference, 2003

2002

A novel and efficient timing-driven global router for standard cell layout design based on critical network concept.

[BibT_eX]

[DOI]

Proceedings of the 2002 International Symposium on Circuits and Systems, 2002

Tong Jing

Timeline

Legend:

Links

On csauthors.net:

Bibliography

Loading...