Koichi Sasada

According to our database, Koichi Sasada authored at least 11 papers between 2003 and 2019.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2019

Gradual write-barrier insertion into a Ruby interpreter.

Koichi Sasada

Proceedings of the 2019 ACM SIGPLAN International Symposium on Memory Management, 2019

2011

A decentralized access control mechanism using authorization certificate for distributed file systems.

Jumpei Arakawa, Koichi Sasada

Proceedings of the 6th International Conference for Internet Technology and Secured Transactions, 2011

2006

A Model of Implementable SMT Processor on FPGA.

Ippei Tate, Yoshiyasu Ogasawara, Mikiko Sato, Koichi Sasada, Kaname Uchikura, Kazunari Asano, Satoshi Watanabe, Mitaro Namiki, Hironori Nakajo

Proceedings of the International Conference on Parallel and Distributed Processing Techniques and Applications & Conference on Real-Time Computing Systems and Applications, 2006

Towards Reconfigurable Cache Memory for a Multithreaded Processor.

Yoshiyasu Ogasawara, Ippei Tate, Satoshi Watanabe, Mikiko Sato, Koichi Sasada, Kaname Uchikura, Kazunari Asano, Mitaro Namiki, Hironori Nakajo

Proceedings of the International Conference on Parallel and Distributed Processing Techniques and Applications & Conference on Real-Time Computing Systems and Applications, 2006

2005

Development of a Thread Scheduler for SMT Processor Architecture.

Kaname Uchikura, Koichi Sasada, Mikiko Sato, Masanori Yamato, Norito Kato, Hironori Nakajo, Mitaro Namiki

Proceedings of the International Conference on Parallel and Distributed Processing Techniques and Applications, 2005

A New Model of Reconfigurable Cache for an SMT Processor and its FPGA Implementation.

Yoshiyasu Ogasawara, Norito Kato, Masanori Yamato, Mikiko Sato, Koichi Sasada, Kaname Uchikura, Mitaro Namiki, Hironori Nakajo

Proceedings of the International Conference on Parallel and Distributed Processing Techniques and Applications, 2005

YARV: yet another RubyVM: innovating the ruby interpreter.

Koichi Sasada

Proceedings of the Companion to the 20th Annual ACM SIGPLAN Conference on Object-Oriented Programming, 2005

2004

Dynamic Allocation of Physical Register Banks for an SMT Processor.

Norito Kato, Masanori Yamato, Osamu Tujimoto, Mikiko Sato, Koichi Sasada, Kaname Uchikura, Mitaro Namiki, Hironori Nakajo

Proceedings of the International Conference on Parallel and Distributed Processing Techniques and Applications, 2004

2003

A Process and Thread Management of the Operating System "Future" for On Chip Multithreaded Architecture.

Mikiko Sato, Koichi Sasada, Shoji Kawahara, Norito Kato, Masanori Yamato, Hironori Nakajo, Mitaro Namiki

Proceedings of the International Conference on Parallel and Distributed Processing Techniques and Applications, 2003

Implementation and Evaluation of a Thread Library for Multithreaded Architecture.

Koichi Sasada, Mikiko Sato, Shoji Kawahara, Norito Kato, Masanori Yamato, Hironori Nakajo, Mitaro Namiki

Proceedings of the International Conference on Parallel and Distributed Processing Techniques and Applications, 2003

Performance Evaluation of an On-Chip Multi-Threaded Processor with Cache Memory Managed by Logical Thread Number.

Hironori Nakajo, Masanori Yamato, Shoji Kawahara, Norito Kato, Koichi Sasada, Mikiko Sato, Mitaro Namiki

Proceedings of the International Conference on Parallel and Distributed Processing Techniques and Applications, 2003