Mitaro Namiki

According to our database1, Mitaro Namiki authored at least 59 papers between 1991 and 2019.

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Bibliography

2019
A Software-based NVM Emulator Supporting Read/Write Asymmetric Latencies.
CoRR, 2019

2018
Reactive NaN Repair for Applying Approximate Memory to Numerical Applications.
CoRR, 2018

OpenCL Runtime for OS-Driven Task Pipelining on Heterogeneous Accelerators.
Proceedings of the 24th IEEE International Conference on Embedded and Real-Time Computing Systems and Applications, 2018

TEE-KV: Secure Immutable Key-Value Store for Trusted Execution Environments.
Proceedings of the ACM Symposium on Cloud Computing, 2018

2017
Towards write-back aware software emulator for non-volatile memory.
Proceedings of the IEEE 6th Non-Volatile Memory Systems and Applications Symposium, 2017

Building block operating system for 3D stacked computer systems with inductive coupling interconnect.
Proceedings of the International SoC Design Conference, 2017

Building block multi-chip systems using inductive coupling through chip interface.
Proceedings of the International SoC Design Conference, 2017

2016
An Operating System Guided Fine-Grained Power Gating Control Based on Runtime Characteristics of Applications.
IEICE Transactions, 2016

2015
A Fine-Grained Power Gating Control on Linux Monitoring Power Consumption of Processor Functional Units.
IEICE Transactions, 2015

2014
Design of Multiple PVAS on InfiniBand Cluster System Consisting of Many-core and Multi-core.
Proceedings of the 21st European MPI Users' Group Meeting, 2014

Multithreaded Two-Phase I/O: Improving Collective MPI-IO Performance on a Lustre File System.
Proceedings of the 22nd Euromicro International Conference on Parallel, 2014

Unbalanced buffer tree synthesis to suppress ground bounce for fine-grain power gating.
Proceedings of the 2014 International Symposium on System-on-Chip, 2014

pmqFlow: Design of propagation time measuring QoS system with OpenFlow for process automation.
Proceedings of the IECON 2014 - 40th Annual Conference of the IEEE Industrial Electronics Society, Dallas, TX, USA, October 29, 2014

First results of performance comparisons on many-core processors in solving QAP with ACO: kepler GPU versus xeon PHI.
Proceedings of the Genetic and Evolutionary Computation Conference, 2014

Design and evaluation of fine-grained power-gating for embedded microprocessors.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014

A fine grained power management supported by just-in-time compiler.
Proceedings of the 2014 IEEE Symposium on Low-Power and High-Speed Chips, 2014

Design and control methodology for fine grain power gating based on energy characterization and code profiling of microprocessors.
Proceedings of the 19th Asia and South Pacific Design Automation Conference, 2014

2013
A Scalable 3D Heterogeneous Multicore with an Inductive ThruChip Interface.
IEEE Micro, 2013

Fine-Grained Run-Tume Power Gating through Co-optimization of Circuit, Architecture, and System Software Design.
IEICE Transactions, 2013

Improving Parallel I/O Performance Using Multithreaded Two-Phase I/O with Processor Affinity Management.
Proceedings of the Parallel Processing and Applied Mathematics, 2013

A Delegation Mechanism on Many-Core Oriented Hybrid Parallel Computers for Scalability of Communicators and Communications in MPI.
Proceedings of the 21st Euromicro International Conference on Parallel, 2013

Demonstration of a heterogeneous multi-core processor with 3-D inductive coupling links.
Proceedings of the 23rd International Conference on Field programmable Logic and Applications, 2013

A scalable 3D heterogeneous multi-core processor with inductive-coupling thruchip interface.
Proceedings of the 2013 IEEE Symposium on Low-Power and High-Speed Chips, 2013

Hardware support for resource partitioning in real-time embedded systems.
Proceedings of the 2013 IEEE Symposium on Low-Power and High-Speed Chips, 2013

2012
Geyser.
Proceedings of the Handbook of Energy-Aware and Green Computing - Two Volume Set., 2012

An OpenCL Runtime Library for Embedded Multi-Core Accelerator.
Proceedings of the 2012 IEEE International Conference on Embedded and Real-Time Computing Systems and Applications, 2012

Delegation-Based MPI Communications for a Hybrid Parallel Computer with Many-Core Architecture.
Proceedings of the Recent Advances in the Message Passing Interface, 2012

An Efficient Kernel-Level Blocking MPI Implementation.
Proceedings of the Recent Advances in the Message Passing Interface, 2012

Dynamic power control with a heterogeneous multi-core system using a 3-D wireless inductive coupling interconnect.
Proceedings of the 2012 International Conference on Field-Programmable Technology, 2012

CMA-Cube: A scalable reconfigurable accelerator with 3-D wireless inductive coupling interconnect.
Proceedings of the 22nd International Conference on Field Programmable Logic and Applications (FPL), 2012

2011
Cool Mega-Arrays: Ultralow-Power Reconfigurable Accelerator Chips.
IEEE Micro, 2011

Design and Implementation Fine-grained Power Gating on Microprocessor Functional Units.
IPSJ Trans. System LSI Design Methodology, 2011

A Leakage Efficient Data TLB Design for Embedded Processors.
IEICE Transactions, 2011

A Leakage Efficient Instruction TLB Design for Embedded Processors.
IEICE Transactions, 2011

CS Unplugged Assisted by Digital Materials for Handicapped People at Schools.
Proceedings of the Informatics in Schools. Contributing to 21st Century Education, 2011

Acceleration experiment of genetic computations for sudoku solution on multi-core processors.
Proceedings of the 13th Annual Genetic and Evolutionary Computation Conference, 2011

Cool Mega-Array: A highly energy efficient reconfigurable accelerator.
Proceedings of the 2011 International Conference on Field-Programmable Technology, 2011

SLD-1(Silent Large Datapath): A ultra low power reconfigurable accelerator.
Proceedings of the 2011 IEEE Symposium on Low-Power and High-Speed Chips, 2011

Geyser-2: The second prototype CPU with fine-grained run-time power gating.
Proceedings of the 16th Asia South Pacific Design Automation Conference, 2011

2010
Adaptive power gating for function units in a microprocessor.
Proceedings of the 11th International Symposium on Quality of Electronic Design (ISQED 2010), 2010

Reducing instruction TLB's leakage power consumption for embedded processors.
Proceedings of the International Green Computing Conference 2010, 2010

Proposal of a multi-core processor architecture for effective evolutionary computation.
Proceedings of the Genetic and Evolutionary Computation Conference, 2010

Proposal of a multi-core processor from the viewpoint of evolutionary computation.
Proceedings of the IEEE Congress on Evolutionary Computation, 2010

Geyser-1: a MIPS R3000 CPU core with fine-grained run-time power gating.
Proceedings of the 15th Asia South Pacific Design Automation Conference, 2010

2009
Design and Implementation of Fine-Grain Power Gating with Ground Bounce Suppression.
Proceedings of the VLSI Design 2009: Improving Productivity through Higher Abstraction, 2009

A CS unplugged design pattern.
Proceedings of the 40th SIGCSE Technical Symposium on Computer Science Education, 2009

Green Multicore-SoC Software-Execution Framework with Timely-Power-Gating Scheme.
Proceedings of the ICPP 2009, 2009

2008
A fine-grain dynamic sleep control scheme in MIPS R3000.
Proceedings of the 26th International Conference on Computer Design, 2008

2007
Mobile Thin-Client System with Fault Tolerance and Scalability by "HTTP-FUSE-KNOPPIX-BOX".
Proceedings of the International Conference on Parallel and Distributed Processing Techniques and Applications, 2007

2006
A Model of Implementable SMT Processor on FPGA.
Proceedings of the International Conference on Parallel and Distributed Processing Techniques and Applications & Conference on Real-Time Computing Systems and Applications, 2006

Towards Reconfigurable Cache Memory for a Multithreaded Processor.
Proceedings of the International Conference on Parallel and Distributed Processing Techniques and Applications & Conference on Real-Time Computing Systems and Applications, 2006

Implementation of PC Cluster System with Memory Mapped File by Commodity OS.
Proceedings of the International Conference on Parallel and Distributed Processing Techniques and Applications & Conference on Real-Time Computing Systems and Applications, 2006

2005
Development of a Thread Scheduler for SMT Processor Architecture.
Proceedings of the International Conference on Parallel and Distributed Processing Techniques and Applications, 2005

A New Model of Reconfigurable Cache for an SMT Processor and its FPGA Implementation.
Proceedings of the International Conference on Parallel and Distributed Processing Techniques and Applications, 2005

2004
Dynamic Allocation of Physical Register Banks for an SMT Processor.
Proceedings of the International Conference on Parallel and Distributed Processing Techniques and Applications, 2004

2003
A Process and Thread Management of the Operating System "Future" for On Chip Multithreaded Architecture.
Proceedings of the International Conference on Parallel and Distributed Processing Techniques and Applications, 2003

Implementation and Evaluation of a Thread Library for Multithreaded Architecture.
Proceedings of the International Conference on Parallel and Distributed Processing Techniques and Applications, 2003

Performance Evaluation of an On-Chip Multi-Threaded Processor with Cache Memory Managed by Logical Thread Number.
Proceedings of the International Conference on Parallel and Distributed Processing Techniques and Applications, 2003

1991
Programming in a mother tongue: philosophy, implementation, practice and effect.
Proceedings of the Fifteenth Annual International Computer Software and Applications Conference, 1991


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