Norito Kato

According to our database1, Norito Kato authored at least 6 papers between 2003 and 2005.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Bibliography

2005
Development of a Thread Scheduler for SMT Processor Architecture.
Proceedings of the International Conference on Parallel and Distributed Processing Techniques and Applications, 2005

A New Model of Reconfigurable Cache for an SMT Processor and its FPGA Implementation.
Proceedings of the International Conference on Parallel and Distributed Processing Techniques and Applications, 2005

2004
Dynamic Allocation of Physical Register Banks for an SMT Processor.
Proceedings of the International Conference on Parallel and Distributed Processing Techniques and Applications, 2004

2003
A Process and Thread Management of the Operating System "Future" for On Chip Multithreaded Architecture.
Proceedings of the International Conference on Parallel and Distributed Processing Techniques and Applications, 2003

Implementation and Evaluation of a Thread Library for Multithreaded Architecture.
Proceedings of the International Conference on Parallel and Distributed Processing Techniques and Applications, 2003

Performance Evaluation of an On-Chip Multi-Threaded Processor with Cache Memory Managed by Logical Thread Number.
Proceedings of the International Conference on Parallel and Distributed Processing Techniques and Applications, 2003


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